Help me understand PLL application

pll application

Hi all,
When I am reading a paper, I am puzzled with a paragraph about PLL application.Here is my question and the paragraph. Thanks!

[My questions]
1)What does the FM modulation mean in the following paragraph? How it cause reference spur? Why not consider this issue when PLL is used as a clock generator?
2)Why not consider the reference spur in clock generator? Is there any different design consideration between frequency synthesizer and clock generator?

[reference paragraph]
When the PLL is used as a digital clock generator for highspeed I/O interfaces, minimizing the clock skew between the internal clock and the external clock is important to get the maximum data bandwidth and the clock skew is mainly determined by the non-ideal charge pump. In frequency synthesis, the charge pump is the dominant block that determines the level of the unwanted FM modulation causing the reference spur.

Re: PLL application issues

actually in frequency synthesizer vco works at high frequency and when a low freuency reference signal comes through charge pump then vco frequency works as carrier freuency, that will modulate the referrence signal. modulation is of both type AM and PM . but phase modulation is dominated. because of this modulation reference spur comes into picture. that will degrade the performence of the system

Re: PLL application issues

Hi us1710,
Thank you four your reply. However, I suppose the PFD/CP is ideal, it seems the AM and FM still exist as you said.(since reference frequency and vco frequency are different). The paragraph I posted say,
the charge pump is the dominant block that determines the level of the unwanted FM modulation causing the reference spur.

How will CP's non-ideal cause FM modulation?
If CP is ideal, does the FM & AM exist?

Best wishes,

Re: PLL application issues

your pfd will work for certain reference frequency. according to that your control signal changes . i mean your control signal changes after the same interval or time period that reference signal has. that is why i think FM modulation comes . for any query u can mail me at us1710@gmail.com

Re: PLL application issues

who can tell me how to slimulation the pll's jitter and phase noise.i use the model don't have the noise parameter.

Re: PLL application issues

simular question i have put, but did not get any reply. so if nebody knows abt it then plz send ur reply.

Re: PLL application issues

dasong said:

who can tell me how to slimulation the pll's jitter and phase noise.i use the model don't have the noise parameter.

Click to expand...

in reality ,few models from foundrise is accurate.