Help me understand an issue with circuit for bandgap startup

[ccw27]

Help on Bandgap Startup

For the startup circuit below used for bandgap I have found that for a fast ramping of supply voltage (10us) it takes a while for the bandgap voltage to reach steady state >10us, under different corners. However if you put a MOS cap at the current mirror this issue is solved. Can anyone explain why is this so? For slow ramping (5ms) of supply voltage the settling time is not an issue.

Thanks

 

[nxing]

Help on Bandgap Startup

probobly you need to draw the whole circuit in, so somebody can help.

 

[dsjomo]

Help on Bandgap Startup

Where you add the cap?

If you add a cap C shunted to the R, the C and CgsMS would form a capacitive divider, this turn on the MS and make the bandgap start faster then charge MS through R.

 

[ccw27]

Re: Help on Bandgap Startup

You put the cap on the gate of the current mirror. In fact if you put cap to the gate of MS you would make things worse. It takes even longer to turn on the NMOS since higher C means longer time to charge.

probobly you need to draw the whole circuit in, so somebody can help.

The rest of the circuit is just a conventional bandgap where the startup circuit pulls the PMOS gate of bandgap so I=0 is avoided.


Thanks

Added after 1 hours 35 minutes:

To clarify, the 10us means I ramp Vdd from 0 to 2.8V in 10us. What I noticed from the simulation is that MS transistor keeps turning on/off in the beginning so that's why its takes longer for the bandgap voltage to reach steady state. But when I put a capacitor at the gate of the startup current mirror this issue is solved.

I believe it has to do with the inital charging of Vgs in the current mirror, putting a capacitor (the larger the better) at the gate delays the startup of Vgs. Because without the capacitor the Vgs starts to charge as soon as Vdd starts to ramp whereas it delays when I put the capacitor there.

Note: This problem only applies for fast ramp of supply voltage. For 10ms ramp there is no need for capacitor.

Thanks

 

[dsjomo]

Re: Help on Bandgap Startup

You charge the CgsMS through R, so if you delay the charging of Cgs of current mirror, the current that charges CgsMS through R is larger. Because less current leakage to current mirror.

When you start to ramp up, MS is on and the current of bandgap grows, then this enlarges the current in your start-up circuit's current mirror. Unfortunatly, the latter draws more current through R that meant to charge MS. So if you delay the current of current mirror, MS is charged faster.

By the way, shouldn't we apply a step function(i mean a shorter rise time under SPICE) for the vdd to simulate the start-up of bandgap??

 

[ccw27]

Re: Help on Bandgap Startup

thanks dsjomo,

Just to make sure, so what you are saying is that adding the cap at the gate of the current mirror allows time for MS to inject charge before the current mirror disrupts the charging of MSCgs. Also for resistor I am using a long channel PMOS bias using Vdd_bar (inverted version of Vdd).

Also you recommend even shorter rise time simulation for Vdd ramp?


Thanks

 

[dsjomo]

Help on Bandgap Startup

Yes, my suggestion is applying a sharp step function to the Vdd, and measure the rise time of the bandgap. And design the bandgap until the rise time is short enough to meet your need.

 

[ccw27]

Re: Help on Bandgap Startup

Besides adding a MOS cap at the gate of the current mirror I also added a larger MOS cap at the gate of MS. This was to reduce the spike when the bandgap goes from power down to up. Can anyone see any cause of concern in adding this two caps? In simulation everything seems ok.

Also why do you want to ramp the vdd faster than 10us? Does ramping vdd faster a harsher test to see whether your startup circuit works? Also what is a good test to check the stability of the OP in bandgap?

Thanks