Help me troubleshoot a problem in LDO design

[mary12]

Hello Everyone, Can anyone help me troubleshooting the problem of LDO design? We design a 3.3V/2.5V DC/DC, but the test result of the DC/DC shows that the output voltage decrease as the output load current increase. By the way ,we use external cap compensation scheme, The LDO can telerate 60mA current load as we designed and the simulation result is correct.
pls see the chart below
Vout (V) Iout (mA)
2.4 2.9
2.23 8.7
2.17 10.8
1.91 19.9
1.8 25.5
1.76 30

Thanks in advance.

 

[VVV]

Re: LDO test

Clearly the regulator is not working properly. You can always expect some voltage drop as the current increases, but the voltage should stay within regulation limits.
Your regulator behaves like it has a very large output resistance.
Can you post the schematic?

 

[mary12]

Re: LDO test

Many thanks VVV, I have post the schematic, pls help me to check it.

 

[VVV]

Re: LDO test

I could not see anything wrong with the schematic.
The only thing I am wondering about is if you have enough headroom to drive the output transistor.

 

[lodestar]

Re: LDO test

post me the schematic,maybe I can help you！

 

[johnsmith101]

Re: LDO test

I plotted the output voltage vs. the output current in excel and it's a straight line. This means that you're in dropout (pass FET needs to be larger).