[SOLVED] Help me to fix these two errors in this VHDL code

dumindu89 · Nov 9, 2012

I am getting following 2 errors when I am compiling my VHDL code.

Error (10621): VHDL Use Clause error at final.vhdl(27): more than one Use Clause imports a declaration of simple name "unsigned" -- none of the declarations are directly visible
Info (10499): VHDL information at numeric_std.vhd(65): object "unsigned" is declared here
Info (10609): VHDL information at syn_arit.vhd(26): duplicate match
Error (10405): VHDL error at final.vhdl(27): can't determine type of object at or near identifier "to_integer" -- found 0 possible types
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Info: Allocated 153 megabytes of memory during processing
Error: Processing ended: Fri Nov 09 07:14:42 2012
Error: Elapsed time: 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 2 errors, 0 warnings

Here is the code. (I highlighted the line that causing these errors)

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
use IEEE.NUMERIC_STD.ALL;

entity final is
port(   clk_in_for_fixed,clk_in_for_programmable,a,b: in std_logic;
        fixed_clk_out,clk_out_programmable,qa,qb: out std_logic;
        programmable_divide_value : in std_logic_vector (10 downto 0)
        );
end final;

architecture Behavioral of final is

 component d2 port 
          ( inpu_c, d_in,reset:in std_logic ;
            q_out  :buffer std_logic 
          ); 
 end component d2; 

signal fixed_divide,counter_programmable,counter_fixed,programmable_divide : integer := 0;
signal set_high, qa_int, qb_int,res :std_logic;                 

begin
fixed_divide <= 2000;
[COLOR=#ff0000][B]programmable_divide <= to_integer(unsigned(programmable_divide_value(10 downto 0)));[/B][/COLOR]

process(clk_in_for_fixed)
begin

    if( rising_edge(clk_in_for_fixed) ) then
        if(counter_fixed < fixed_divide/2-1) then
            counter_fixed <= counter_fixed + 1;
             fixed_clk_out <= '0';

        elsif(counter_fixed < fixed_divide-1) then
            counter_fixed <= counter_fixed + 1;
            fixed_clk_out <= '1';

        else
             fixed_clk_out <= '0';
            counter_fixed <= 0;
        end if;
    end if;
end process;

process(clk_in_for_programmable)
begin

if( rising_edge (clk_in_for_programmable))then
        if(counter_programmable< programmable_divide/2-1) then
            counter_programmable <= counter_programmable+ 1;
            clk_out_programmable <= '0';

        elsif(counter_programmable < programmable_divide-1) then
            counter_programmable <= counter_programmable+ 1;
             clk_out_programmable<= '1';
        else
            clk_out_programmable <= '0';
            counter_programmable <= 0;
        end if;
    end if;
  
end process;
          
 set_high <= '1';
 
d0: d2 port map (
    inpu_c => a,
    reset => res,
    d_in   => set_high,
    q_out  => qa_int
    );
               
d1: d2 port map (
    inpu_c => b,
    reset => res,
    d_in   => set_high,
    q_out  => qb_int
    );

res <= qb_int and qa_int;

qa <= qa_int;
qb <= qb_int; 


end Behavioral;

The code of the other VHDL file that I have added to this project is shown below.

Code VHDL - [expand]
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library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
 
 
entity d2 is 
    port (inpu_c, d_in, reset :in std_logic ;
          q_out  :buffer std_logic 
         ); 
end d2;       
     
-- output is assigned to the input 
-- at the clcok edge
architecture archd2 of d2 is 
    begin 
    dflop:process (inpu_c, reset)
 
 
    begin 
          if reset = '1' then 
             q_out <= '0';
          elsif  inpu_c 'event and inpu_c = '1' then 
              q_out <= d_in;
           end if; 
    end process dflop; 
end archd2;

What is the problem with my code?

K-J · Nov 9, 2012

Delete the following two lines:

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

There is no declaration for 'programmable_divide' so you didn't post everything...I'm assuming that it must be declared as an integer since it is assigned by the output of the to_integer() function

Kevin Jennings

ads_ee · Nov 9, 2012

Code:

use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;

I'm pretty sure your problem is due to having both libraries called out. Remove the obsolete std_logic_arith here and in your tb.

Regards,
-alan

[SOLVED] Help me to fix these two errors in this VHDL code

dumindu89

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K-J

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dumindu89

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[SOLVED] Help me to fix these two errors in this VHDL code

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