Help me to fix my counter code (Modelsim simulation)

the following is source code.I think the count should be 8,16......at the
St8_1,but the simulation result is 16,32......,why?
(use modelsim simulation)
library ieee;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Unsigned.all;
use IEEE.Std_Logic_Arith.all;

entity teststate is
port
(
SysClk : in Std_Logic; --timer
Reset : in std_logic
);
end teststate;

architecture Action of teststate is

type State_1 is (St0_1, St1_1, St2_1, St3_1, St4_1, St5_1,St6_1,St7_1,St8_1);
signal Cur_State_1, Next_State_1:State_1 := St0_1;
signal count : integer range 0 to 128;

begin

process(SysClk,ReSet)
begin
if Reset = '0' then
count <= 0;
elsif rising_edge(SysClk) then
case Cur_State_1 is
when St0_1 => Next_State_1 <= St1_1;
count <= count + 1;
when St1_1 => Next_State_1 <= St2_1;
count <= count + 1;
when St2_1 => Next_State_1 <= St3_1;
count <= count + 1;
when St3_1 => Next_State_1 <= St4_1;
count <= count + 1;
when St4_1 => Next_State_1 <= St5_1;
count <= count + 1;
when St5_1 => Next_State_1 <= St6_1;
count <= count + 1;
when St6_1 => Next_State_1 <= St7_1;
count <= count + 1;
when St7_1 => Next_State_1 <= St8_1;
count <= count + 1;
when St8_1 => Next_State_1 <= St0_1;
count <= count + 1;
when others => Next_State_1 <= St0_1;
end case;
end if;
end process;

process(Reset, SysClk)
begin
if Reset = '0' then
Cur_State_1 <= St0_1;
elsif rising_edge(SysClk) then
Cur_State_1 <= Next_State_1;
end if;
end process;

end Action;

Re: please help me!thx

Check with the following code!