[SOLVED] Help me to code Parallel MAC unit in verilog.

Status
Not open for further replies.

gstekboy

Member level 5
Joined
Oct 18, 2013
Messages
87
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Visit site
Activity points
512
My parallel MAC unit design is given below.


I have codes for accumulator , booth encoder..etc

Now problem is how to combine this in parallel? can anyone help.

ieee paper is attached below.

View attachment 05337888_2.pdf
 

Now problem is how to combine this in parallel? can anyone help.

What do you mean by combine in parallel? Do you mean you want to implement the partial product summation as a parallel implementation? If so then expect the design to have a very low clock period. The design should be done as the block diagram shows and Fig3 Proposed arithmetic operations shows, using a pipeline registers between blocks and registering the the partial product summation accumulation.
 

you can write your code in any HDL language it does not matter in which language you implement it.
Yes ads-ee is right.To get appropriate clock frequency you must form a pipeline based on your design.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…