Help me the holdtime problem

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In a flip flop like this,anyone can tell me how is the hold time violation come from?
when clk=1,the first tran_mos is off, how can the input D effect the output Q?


 

can u pls put hte diagram bit more clearly ...
so that its easy to understand !!!
 

suppose the clk changes at the 2nd transistor before the clk at the 1st transistor (they will not change simultaneously). Also, suppose the D input changes just before clk->1.
 

sorry, i have redrawn the diagram.
when the clk=0, input d is stored in the first inverter loop. it need some time to go to stable before the clk=1, this is the setup time.
But how about the holdtime? when the clk=1,the first tran_cmos is turned off, why the input data d shoud be stable after the clk=1.
 

"But how about the holdtime? when the clk=1,the first tran_cmos is turned off, why the input data d shoud be stable after the clk=1."
I suppose that this is because of the propagation time that is required by the following combinational logic circuit.
 

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