help me,some problems about S/H circuit

[winsonpku]

site:www.edaboard.com s/h

i am designing a S/H circuit.which is used in the 14-bit pipeline ADC.the main parameter : the AMP dc gain=104db, GBW=160MHz. sampling capacitor=13p.
and the S/H's load=14p.the S/H circuit's architecture is flip-around（the architecture is referenced in this paper:A 3-v 340-mw 14-b 75-Msaple/s CMOS ADC with 85-db SFDR at Nyquist input).but now i have two prolems:
1):at the hold phase,the sampling result is always not as the expected result.
2):at the hold phase,the sampling result is falling down.but when the input is small,the result is retaining,and dosen't fall down,i guess this maybe for the common-mode range is too samll?!
otherwise,the input port of the AMP always will gitch when the hold phase clock is starting. this is not for the switch,when i use ideal switch,the phenomenon still exist.
then what is the reason.
i attempt to use the ideal AMP,but the hspice always tell the internal step is too small.i use the decription :Eamp outn outp opamp inn inp
thanks first!

 

[Btrend]

my suggestion,
1. check the ideal opamp first, run AC , TRAN with step response and feedback including.
2. check the opamp u designed carefully, do (1) again
3. check ur non-overlapped clock, especially the sequence of clocks

 

[winsonpku]

first,i use the ideal opamp,but it doesn't work,i mean when do the hspice simulation,it always tell me the internal time step is too small.i know the ideal opamp's descrition must be wrong,but after i refered the hspice manual,i still can't know what is the right description.
second,the opamp i designed,the simulation is successful.the dc gain=104db,phase magin=72 gbw=160Mhz these result satisfied my design.
last,the clock's sequence is right too.
thanks for your help.

my suggestion,
1. check the ideal opamp first, run AC , TRAN with step response and feedback including.
2. check the opamp u designed carefully, do (1) again
3. check ur non-overlapped clock, especially the sequence of clocks

 

[nxing]

Coul you please post some of your simulation results here, in that way, it will be easier to help you out.

 

[ezt]

Hi.
I had this problem lots of times. Sometime this problem appears because of CMFB. I mean maybe the CMFB of your circuit can't work properly for whole ouput voltage swing. So for larger swing, the gain of your circuit is not large enough and hence there's a big ess in output. Maybe your answer is "But I have simulated its CMFB response in open-loop form and that works good." But it should work so good in closed-loop form too. use ideal CMFB circuit first. If your problem vanishes, so it's that case!

Regards,
EZT

 

[codec]

You have not checked the AC (small signal) performance of your AMP. However, your problem is related to TR (large signal) response. You can first do the settling simulation using your AMP.

 

[winsonpku]

i also thought maybe for the common-mode range issue,you gave me a good advice,i will use the ideal cmfb to do the simulation.thanks again!

Hi.
I had this problem lots of times. Sometime this problem appears because of CMFB. I mean maybe the CMFB of your circuit can't work properly for whole ouput voltage swing. So for larger swing, the gain of your circuit is not large enough and hence there's a big ess in output. Maybe your answer is "But I have simulated its CMFB response in open-loop form and that works good." But it should work so good in closed-loop form too. use ideal CMFB circuit first. If your problem vanishes, so it's that case!

Regards,
EZT

 

[winsonpku]

i have simulated the AC perfomace of my AMP at the open loop and i found the dc gain and phase margin is the same as i designed.so i don't understand what is your meaning of " AC performance".

You have not checked the AC (small signal) performance of your AMP. However, your problem is related to TR (large signal) response. You can first do the settling simulation using your AMP.

 

[winsonpku]

for my company's poor net,i have tried so many times to post my simulation,but i can't succeed.

Coul you please post some of your simulation results here, in that way, it will be easier to help you out.