SVTONY
Member level 1
characterizing memory current leakage with hsim
I have a design which I found uses excessive current while in
suspend mode when clock is turned off. Is there any good tool
that can help me catch the problem? RTL level or transistor
level will be just fine. Of course I didn't want to run HSPICE.
Thanks!
I have a design which I found uses excessive current while in
suspend mode when clock is turned off. Is there any good tool
that can help me catch the problem? RTL level or transistor
level will be just fine. Of course I didn't want to run HSPICE.
Thanks!