Help me solve an error in cache unit code in VHDL

error_cache

I try to design a cache unit on vhdl but xilinx have a mesage that some signal cannot synthesized.Is anyone who know what is the problem?????
My code is bellow :


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity InsCache is
generic( depth: integer:=8); -- index size 8
port(Clock, Clear : in std_logic;
L1Hit,L1Miss,Stall : out std_logic;
ReadyL2Ins :in std_logic;
InstrAddr: in std_logic_vector(31 downto 0);
InstrBus : out std_logic_vector(31 downto 0);
L2Bus: in std_logic_vector(31 downto 0)
);
end InsCache;

architecture Behavioral of L1InsCache is

-- cache array
type cache_type is array (0 to depth-1) of std_logic_vector(31 downto 0);

-- tag bits
type tag_type is array (0 to depth-1) of std_logic_vector(3 downto 0);

-- valid bits
type valid_type is array (0 to depth-1) of std_logic;


signal cache : cache_type :=(
X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000");

signal tag : tag_type :=(
X"0",X"0",X"0",X"0",
X"0",X"0",X"0",X"0");

signal val : valid_type :=(
'0','0','0','0',
'0','0','0','0');

--tag 8 to 5
--index 4 to 2
--byteoffset 1 to 0

begin

process(Clear,Clock,InstrAddr,ReadyL2Ins,L2Bus)
variable a : integer;
begin
if Clear='1'
then
InstrBus <= X"00000000";
L1Miss<='0';
L1Hit<='0';
elsif Clock<='1' then
a:=conv_integer(InstrAddr(4 downto 2));
if (val(a)='1' and InstrAddr(8 downto 5)=tag(a))
then
InstrBus<=cache(a);
L1Hit<='1';
report "L1 Inst hit";
L1Miss<='0';
Stall<='0';
else
L1Hit<='0';
L1Miss<='1';
report "L1 Inst miss";

if ReadyL2Ins='1' and rising_edge(Clock)
then
InstrBus<=L2Bus;
Stall<='0';
a:=conv_integer(InstrAddr(4 downto 2));
cache(a)<=L2Bus;
tag(a) <=InstrAddr(8 downto 5);
val(a) <='1';
else
Stall<='1';
end if;
end if;
end if;
end process;
end Behavioral;