Help me solve a syntax error in 4 bit CLA adder

4 BIT CLA ADDER HELP!

Hey guys for some reason I have been working on this adder for the past few days and can not get this thing to compile. I am getting an Error: Line 49: VHDL syntax error; unexpected end-of-file. What does this mean? I can't find where the error is.

library ieee;
use ieee.std_logic_1164.all;

ENTITY CLA_ADDER IS
PORT (x0, x1, x2, x3 : in std_logic;
y0, y1, y2, y3 : in std_logic;
c0 : in std_logic;
s0, s1, s2, s3 : out std_logic);
END CLA_ADDER;

Architecture behavior OF CLA_ADDER IS
Signal g0, g1, g2, g3, p0, p1, p2, p3, c1, c2, c3, c4 : Std_logic;

Begin

-- Defining G
Process (x0,x1,x2,x3,y0,y1,y2,y3)
Begin
g0 <= x0 and y0;
g1 <= x1 and y1;
g2 <= x2 and y2;
g3 <= x3 and y3;
-- Defining P
p0 <= x0 or y0;
p1 <= x1 or y1;
p2 <= x2 or y2;
p3 <= x3 or y3;
End Process;


-- Defining C
Process (g0,g1,g2,g3,p0,p1,p2,p3,c0)
Begin
c1 <= g1 or (p1 and c0);
c2 <= g2 or (p2 and (g1 or ( p1 and c0));
c3 <= g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and c0 );
c4 <= g3 or (G3 and G2) or (P3 and P2 and G1) or (P3 and P2 and P1 and G0) or (P3 and P2 and P1 and P0 and C0);
End Process;

-- Defining S
Process (p0,p1,p2,p3,c0,c1,c2,c3);
Begin
s0 <= p0 xor c0;
s1 <= p1 xor c1;
s2 <= p2 xor c2;
s3 <= p3 xor c3;
End process;
END architecture behavior;

Re: 4 BIT CLA ADDER HELP!

You missed a ")" in line 35. Also you put ";" after "process" in line 41. In line 48 you should delete "architecture". Please try the following code:

library ieee;
use ieee.std_logic_1164.all;

ENTITY CLA_ADDER IS
PORT (x0, x1, x2, x3 : in std_logic;
y0, y1, y2, y3 : in std_logic;
c0 : in std_logic;
s0, s1, s2, s3 : out std_logic);
END CLA_ADDER;

Architecture behavior OF CLA_ADDER IS
Signal g0, g1, g2, g3, p0, p1, p2, p3, c1, c2, c3, c4 : Std_logic;

Begin

-- Defining G
Process (x0,x1,x2,x3,y0,y1,y2,y3)
Begin
g0 <= x0 and y0;
g1 <= x1 and y1;
g2 <= x2 and y2;
g3 <= x3 and y3;
-- Defining P
p0 <= x0 or y0;
p1 <= x1 or y1;
p2 <= x2 or y2;
p3 <= x3 or y3;
End Process;


-- Defining C
Process (g0,g1,g2,g3,p0,p1,p2,p3,c0)
Begin
c1 <= g1 or (p1 and c0);
c2 <= g2 or (p2 and (g1 or ( p1 and c0)));
c3 <= g3 or (p3 and g2) or (p3 and p2 and g1) or (p3 and p2 and p1 and c0 );
c4 <= g3 or (G3 and G2) or (P3 and P2 and G1) or (P3 and P2 and P1 and G0) or (P3 and P2 and P1 and P0 and C0);
End Process;

-- Defining S
Process (p0,p1,p2,p3,c0,c1,c2,c3)
Begin
s0 <= p0 xor c0;
s1 <= p1 xor c1;
s2 <= p2 xor c2;
s3 <= p3 xor c3;
End process;
END behavior;