Help me solve a hard logic task

module invert (
               // Outputs
               a_n, b_n, c_n, 
               // Inputs
               a, b, c
               );
   input a,b,c;
   output      a_n, b_n, c_n;
   wire        x1,y1,z1;
   wire [7:0]  d;
// note here that x1 and y1 are complimentory to each other 
// giving us the third missing not get which I used for Muxing 0 or ~7
   
   assign      x1 = ~((a|b) & (b|c) & (c|a));   // 0 1 2 4
   assign      y1 = (a&b)|(b&c)|(c&a);          // 3 5 6 7
   assign      z1 = ~( ((a | b | c) & x1) | ((a & b & c) & y1) ); // mux for 0 and ~7

   // Decoder for 0 to 7
   assign      d[0] = z1 & x1;
   assign      d[1] = x1 & c;
   assign      d[2] = x1 & b;
   assign      d[3] = y1 & (b & c) & z1;
   assign      d[4] = x1 & a;
   assign      d[5] = y1 & (a & c) & z1;
   assign      d[6] = y1 & (a & b) & z1;
   assign      d[7] = (a & b & c);
   // invertor 
   assign a_n = d[0] | d[1] | d[2] | d[3];
   assign b_n = d[0] | d[1] | d[4] | d[5];
   assign c_n = d[0] | d[2] | d[4] | d[6];
   
endmodule // invert


module test();
   reg a,b,c;
   wire        a_n, b_n, c_n;
   invert invert(// Outputs
                 a_n, b_n, c_n, 
                 // Inputs
                 a, b, c
                 );
   initial begin
       $monitor($time,,"abc = %b --> %b  %b %b %b %b %b %b %b %b x1=%b y1=%b",
                {a,b,c},{a_n,b_n,c_n}, invert.d[0],invert.d[1],invert.d[2],invert.d[3],
                invert.d[4],invert.d[5],invert.d[6],invert.d[7], invert.x1, invert.y1);
       {a,b,c} = 3'b000;
       #10;
       {a,b,c} = 3'b001;
       #10;
       {a,b,c} = 3'b010;
       #10;
       {a,b,c} = 3'b011;
       #10;
       {a,b,c} = 3'b100;
       #10;
       {a,b,c} = 3'b101;
       #10;
       {a,b,c} = 3'b110;
       #10;
       {a,b,c} = 3'b111;
       #10;
       $finish;
   end
endmodule // test