We have a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order). How big the fifo needs to be to avoid data over/under-run.
How to solve such FIFO depth problem?
Any suggestions will be appreciated!
Best regards,
Davy
Almost 16 word locations, if considered 80 words each word at 100 mhz and read operation each word at 80 mhz. And about the 80 clks only active in the 100 clks u have to still consider the above 16 word locations as the input and output clk rates different
Is there only one burst of data, or are there multiple consecutive bursts of data?
If there's only one burst of data, then worst case occurs when all 80 words are bunched together. The FIFO inputs 80 words in 800ns. During those same 800ns, the FIFO outputs 64 words. FIFO depth is 80-64=16.
If there are multiple consecutive burst of data, then worst case occurs when 160 words from two packets are all bunched together. The FIFO inputs 160 words in 1600ns. During those same 1600ns, the FIFO outputs 128 words. FIFO depth is 160-128=32.
The FIFO may need a few additional words depending on how you implement the FIFO handshake. (You may write a few words into the FIFO before reading out any words.)
U got the answer from above(echo), Even if there is 80 words of data or less or more in a 100 clk cycles it doesnt matter, It matters only how many words of data you are writing(burst) at a particular clk freq and much is the clk freq on the reading side. It also matters how the read and write enables differentiates. Thanks echo.