Help me set the right parameters of LVDS in 130nm CMOS technology

[abhi_4_u]

Hi,

I am making a LVDS in 130nm CMOS tech.
My Specs are :
275 - 2000mVp-p differential input range ; 400 - 750mVp-p differential output range.
Can any1 plz suggest me that;
1.What should be maximum current for my current mirror (atleast some rough value);
2.What can be my maximum size of PMOS (in current mirror) for the design to be fabricatable.

Its a 2 Gbps design :|

I would really appreciate a quick n positive reply.
Thanks in Advance,
Regards,
Abhi

 

[laglead]

Re: LVDS in 130nm

Generally LVDS output voltage is formed with 3.5mA current flowing through 100ohm termination resistor. So, 350mV is a typical Vp-p. Why your smallest swing is 400mV? That contradict with low swing purpose.

 

[ravet]

Re: LVDS in 130nm

Hi,

I am making a LVDS in 130nm CMOS tech.
My Specs are :
275 - 2000mVp-p differential input range ; 400 - 750mVp-p differential output range.
Can any1 plz suggest me that;
1.What should be maximum current for my current mirror (atleast some rough value);
2.What can be my maximum size of PMOS (in current mirror) for the design to be fabricatable.

Its a 2 Gbps design :|

I would really appreciate a quick n positive reply.
Thanks in Advance,
Regards,
Abhi

i know a friend who made an lvds output buffer, operates till 3Gbps , the matching resistor; 100 ohm, and your desired swing will determine the current flowing, as it was said, around 3.5 mA, concerning the sizes of the pmos devices, it is totally depend on the technology, if it permits or not.. i think i saw a size of 4000/0.4 in a paper, enjoy LVDS