Help me remove glitches from a latch design

[yen]

I am doing thing about latch.
I have a question about glitch like picture.
How can i clear the glitch.
thank you.

Added after 8 minutes:

This is a picture.

 

[Humungus]

Re: Latch question

above all, reduce the size of the image. 2.5 MB is not acceptabe for a simple jpeg

 

[yen]

Re: Latch question

This is a picture

 

[elbadry]

Re: Latch question

I don't think this glitch is a problem...too small to cause any problems I think.

 

[yen]

Re: Latch question

I am doing a thing about 14 bits dac.
This is a thing to control current cell.
It will cause current peak.

 

[eng_Semi]

Re: Latch question

Why u r annoyed by these glitches ?

 

[elbadry]

Re: Latch question

I still see that this glitch is absolutely negligible. You can never get 100% glitch-free circuits I think. If you use this to control a current source or something, I don't think it'll introduce a problem, it's very small compared to the output level.

My advice is try to use this circuit in its place and see the effect of those glitches.

Hope this is useful

 

[yen]

Re: Latch question

This latch controls current cell.
If clk frquency is high, the current will vary with latch.
The current like charge current.
How do i measure the current?
Thank you.

 

[Btrend]

Re: Latch question

This latch controls current cell.
If clk frquency is high, the current will vary with latch.
The current like charge current.
How do i measure the current?
Thank you.

I think what u mean "glitch" is due to ur cross point of the two switchs which are used to switch current cell of ur dac, the glitch is "glitch of current" not " glitch of voltage", right?

 

[nitu]

Re: Latch question

hi...
Ypu can reduce the voltage glitches by using the large capacitors. This glitch that you are opserving will always be there i case it is because of coupling between the gate and drain. To reduce its effect you can add very high capacitor at the output but this will effects your delay and the slope.

I hope this helped
nitu

 

[nile_king]

Re: Latch question

hi...
Ypu can reduce the voltage glitches by using the large capacitors. This glitch that you are opserving will always be there i case it is because of coupling between the gate and drain. To reduce its effect you can add very high capacitor at the output but this will effects your delay and the slope.

I hope this helped
nitu

But the large capacitance will cause slower response
I'm designing also for latches and this small peaks have no effect

 

[kwkam]

Latch question

If you use logic to control current. You better use current source as output. Rather than just CMOS inverter. And I think it should help!

Usually, glitch can't be remove completely. You can think about the settling time of the analog circuits.