Help me pick the architecture of a CDR charge pump

[jxzhang]

Hi,

If the half rate phase detector of a CDR outputs a voltage level from 2.4v ~ 3.2v swing, anyone can suggest me the architecture of charge pump?

many thanks!

 

[eng_Semi]

Re: CDR charge pump

If u can't find a suitable charge pump that operates on this high range, u may shift down the dc voltage of the PD outout

 

[mmohsen]

CDR charge pump

what about your supply voltage ??

 

[layes2]

Re: CDR charge pump

swithing at source
and use opamp

 

[jxzhang]

Re: CDR charge pump

Thanks for replies,
(1) the supply rail is 3.3v
(2) Can u tell me more in detail about swithing at source
and use opamp

It seems that the traditional charge pump (current source with UP DN switches)
needs full swing UP DN signal to on off the switches, so the Phase Detector "MUST" output full swing signals??
If I'm wrong, pls kindly advise me!! Thanks!

 

[mmohsen]

Re: CDR charge pump

swithing at source
and use opamp

i think he means switching @ source and it is one of the switching topologies in CP design [@sorce - @gate - @ drain] and op-amp is used to reduce charge charing.

and about your problem my point of view that u need a level shifter 2.4 >> 0
and 3.2 >> vdd for perfect switching try to see the technique used in CML to CMOS conversion i think u could use somthing like it .

or try to use op-mp as a level discriminator but in this case u will need a constant reference voltage and the op-amp should work near rails as your inputs are both 2.4 and 3.2 > vdd/2 so take care as it will not be straight forward

and try to read this paper it is really very good and will help you in CP desgin

Rhee, W, “Design of High Performance CMOS Charge Pumps in Phase Locked Loop” Proceedings of
the IEEE International Symposium on Circuits and Systems, 1999, Volume: 2, 1999, pp. 545 -548regards,.

 

[jxzhang]

Re: CDR charge pump

Data rate is 1.25Gb/s , so i'm afread of serious delay by level shifter...

anyway, thanks...

 

[mmohsen]

CDR charge pump

the CML to CMOS level shifters could be used for high freq. so i think it could be used with your Data rate although it is high. but you must have some acceptable delay .
would you send me the block digram of your PD !? may be i could help .

best regards,..

 

[eng_Semi]

Re: CDR charge pump

Data rate is 1.25Gb/s , so i'm afread of serious delay by level shifter...

It will depend on the technology used, if u r designing an integrated CDR.

U may simply use a source (or drain) follower which has a unity gain but shift down the dc voltage by Vbe (or Vgs)

 

[jxzhang]

Re: CDR charge pump

Just a hogge type variation half rate PD, like Razavi used.

 

[mmohsen]

Re: CDR charge pump

Just a hogge type variation half rate PD, like Razavi used.

i think you have something not right.
so try to recheck your ciruit or try to use modified Hogge .

regards