Aigneryu
Member level 3
I try to use nc-verilog instead of verilog-XL
but when I type "ncverilog top.v cell.v" as what I did in verilog-XL
the simulator will not launch unless I type "ncverilog top.v cell.v +access+r"
Moreover, if I have to attach a cell based lib cell_lib.v to run simulation,
I write "`uselib file= /path/cell_lib.v" in my netlist, and the verilog-XL runs well, while ncverilog will not run with certain warning messages. In fact, I found that as soon as I put the uselib syntax in my netlist, the ncverilog will not launch.
How can it be like this? Can somebody help me? or show me some examples to use nc-verilog in command line mode.
but when I type "ncverilog top.v cell.v" as what I did in verilog-XL
the simulator will not launch unless I type "ncverilog top.v cell.v +access+r"
Moreover, if I have to attach a cell based lib cell_lib.v to run simulation,
I write "`uselib file= /path/cell_lib.v" in my netlist, and the verilog-XL runs well, while ncverilog will not run with certain warning messages. In fact, I found that as soon as I put the uselib syntax in my netlist, the ncverilog will not launch.
How can it be like this? Can somebody help me? or show me some examples to use nc-verilog in command line mode.