help me in error i found in my vhdl code

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n.mehr

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hello
i Receive this errors
please help me
This is very urgent

** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(50): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(69): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(90): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(90): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(109): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(109): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(11): Nonresolved signal 'd_out' has multiple sources.

and this is my code
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
       
  

entity DualBuffer is
  
  port(d_in : in bit_vector(0 to 7);
        d_out: out bit_vector(0 to 7);
        wr_addr:inout std_logic;
        rd_addr:inout std_logic;
        wr_clk :inout std_logic;
        rd_clk :inout std_logic);
  end entity ;
  
  architecture struct of DualBuffer is
    signal empty,full :bit;
    signal counter1,counter2 : integer:=0;
    signal flag : bit:='1';
    signal wr_en1:std_logic;
    signal wr_en2:std_logic;
    signal rd_en1:std_logic;
    signal rd_en2:std_logic;
    
   
    
    component Ram is
      port( d_in :in bit_vector (0 to 7);
        d_out :out bit_vector(0 to 7);
        wr_clk,rd_clk :inout std_logic ;
        wr_en,rd_en:inout std_logic;
        wr_addr:inout std_logic;
        rd_addr :inout std_logic);
      end component Ram;
      
      begin
        Ram1 : component Ram
        port map (d_in =>d_in,d_out=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        Ram2 :component Ram
        port map (d_in =>d_in ,d_out=>d_out,wr_en=>wr_en2,rd_en=>rd_en2,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        write_read : process is
        begin
          if (rd_clk'event and rd_clk='1' and rd_en1='1') then
              if (wr_en1='0') then
                if (counter1 /=0) then
                d_out <= Ram1(conv_integer(rd_addr));
                counter1<= counter1 -1;
                flag <='0';
               else --Ram1 is empty
                wr_en1 <='1';
                wait for 10 ns;
                rd_en1<= '0';
                wait for 10 ns;
                wr_en2 <='0';
                wait for 10 ns;
                rd_en2<='1';
                wait for 10 ns;
                counter1 <=0;
              end if;
            end if;
          elsif (rd_clk'event and rd_clk='1' and rd_en2='1') then
            if(wr_en2='0') then
              if(counter2 /=0)then
                if (flag /='1')then
                  d_out<=Ram2(conv_integer(rd_addr));
                  counter2<= counter2 -1;
                else --Ram2 is empty
                  rd_en2<= '0';
                  wait for 10 ns;
                  wr_en2<= '1';
                  wait for 10 ns;
                  wr_en1<= '0';
                  wait for 10 ns;
                  rd_en1<= '1';
                  wait for 10 ns;
                  counter2 <=0;
                end if;
              end if;
            end if;
          end if;
        
        
         if(wr_clk'event and wr_clk='1' and wr_en1='1')then
                  if(rd_en1='0')then
                       if(counter1 /=16) then
                             Ram1(conv_integer(wr_addr))<= d_in;
                             counter1<=counter1+1;
                       else --Ram1 is full
                          wr_en1 <='0';
                          wait for 10 ns;
                          rd_en1<='1';
                          wait for 10 ns;
                          wr_en2<='1';
                          wait for 10 ns;
                          rd_en2<='0';
                          wait for 10 ns;
                          counter1<=16;
                          wait for 10 ns;
                       end if;
                  end if;
 
              elsif(wr_clk'event and wr_clk='1' and wr_en2='1')then
                   if(rd_en2='0')then
                       if(counter2 /=16)then
                           Ram2(conv_integer(wr_addr))<=d_in;
                           counter2<=counter2+1;
                       else --Ram2 is full
                          wr_en2 <='0';
                          wait for 10 ns;
                          rd_en2 <='1';
                          wait for 10 ns;
                          wr_en1 <='1';
                          wait for 10 ns;
                          rd_en1 <='0';
                          wait for 10 ns;
                          counter2<=16;
                          wait for 10 ns;
                       end if;
                   end if;
              end if;
         wait on wr_clk,wr_en1,rd_en1,counter1,wr_en2,rd_en2,counter2;
         end process ;
           
           fullempty:process is
           begin
           
           if(rd_en2='1' and wr_en1='1')then
              if(counter1=16 and counter2 /=0) then
                 full<='1';
              end if;
           elsif(rd_en1='1' and wr_en2='1')then
                if(counter1 /=0 and counter2=16)then
                  full<='1';
                end if;
           elsif (rd_en2='1' and wr_en1='1' )then
                if( counter1 /=16 and counter2=0) then
                    empty<= '1';
                end if;
           elsif(rd_en1='1' and wr_en2 ='1') then
               if(counter1=0 and counter2 /=16) then
               empty <='1';
               end if;
           end if;
          wait ;
      end process fullempty;
  end architecture;
    
    configuration conection of DualBuffer is
      for struct
          for Ram1,Ram2:Ram
             use entity work.Dual_Port_Ram(behavior);
           end for;
         end for ;
     end configuration conection ;
please help me
 

you cannot convert a std_logic to an integer, you have to convert it to a std_logic_vector. The easiest way would be to do this:

d_out <= Ram1(conv_integer("" & rd_addr));

a couple of other problems:
1. you have no senstivity lists, this will not work in simulation.
2. you should only use 1 clock in a process. The read and write clock domains should be in their own processes, and you should not use an elsif for the two different rd_en anded with the clock, you should follow this format:

Code: 
if rising_edge(clk) then
  if rd_en1 = '1' then
    ....

  elsif rd_en2 = '1' then
    ....

3. You cannot use waits in synthesisable code - so I assume this is ONLY a simulation model
4. Do you really need a configuration? you only need them if you have more than 1 architecture.
 

i dont Understand
I've isolated process
i use std_logic becuse in errors i see Nonresolved signal.it Was worse
my errors

** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38): Signal "wr_en1" is type ieee.std_logic_1164.std_logic; expecting type std.standard.bit.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38): Signal "rd_en1" is type ieee.std_logic_1164.std_logic; expecting type std.standard.bit.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(41): Signal "wr_en2" is type ieee.std_logic_1164.std_logic; expecting type std.standard.bit.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(41): Signal "rd_en2" is type ieee.std_logic_1164.std_logic; expecting type std.standard.bit.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(49): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(68): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(94): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(94): No feasible entries for subprogram "conv_integer".
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(113): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(113): (vcom-1136) Unknown identifier "conve_integer".
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(10): Nonresolved signal 'd_out' has multiple sources.
Drivers:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(41):Instantiation ram2
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38):Instantiation ram1
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(43)rocess read
Driven at:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(49)
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(11): Nonresolved signal 'wr_addr' has multiple sources.
Drivers:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(41):Instantiation ram2
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38):Instantiation ram1
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(12): Nonresolved signal 'rd_addr' has multiple sources.
Drivers:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(41):Instantiation ram2
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38):Instantiation ram1
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(13): Nonresolved signal 'wr_clk' has multiple sources.
Drivers:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(41):Instantiation ram2
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38):Instantiation ram1
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(14): Nonresolved signal 'rd_clk' has multiple sources.
Drivers:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(41):Instantiation ram2
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(38):Instantiation ram1
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(19): Nonresolved signal 'counter1' has multiple sources.
Drivers:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(43)rocess read
Driven at:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(50)
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(88)rocess write
Driven at:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(95)
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(19): Nonresolved signal 'counter2' has multiple sources.
Drivers:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(43)rocess read
Driven at:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(69)
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(88)rocess write
Driven at:
D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(114)
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(155): VHDL Compiler exiting



my another code
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
  

entity DualBuffer is
  
  port(d_in : in bit_vector(0 to 7);
        d_out: out bit_vector(0 to 7);
        wr_addr:inout bit_vector( 0 to 3);
        rd_addr:inout bit_vector( 0 to 3);
        wr_clk :inout bit;
        rd_clk :inout bit);
  end entity ;
  
  architecture struct of DualBuffer is
    signal empty,full :bit;
    signal counter1,counter2 : integer;
    signal flag : bit:='1';
    signal wr_en1:std_logic;
    signal wr_en2:std_logic;
    signal rd_en1:std_logic;
    signal rd_en2:std_logic;
    
  
    component Ram is
      port( d_in :in bit_vector (0 to 7);
        d_out :out bit_vector(0 to 7);
        wr_clk,rd_clk :inout bit ;
        wr_en,rd_en:inout bit;
        wr_addr:inout bit_vector(0 to 3);
        rd_addr :inout bit_vector(0 to 3));
      end component Ram;
      
      begin
        Ram1 : component Ram
        port map (d_in =>d_in,d_out=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        Ram2 :component Ram
        port map (d_in =>d_in ,d_out=>d_out,wr_en=>wr_en2,rd_en=>rd_en2,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        read : process is
        begin
          if (rd_clk'event and rd_clk='1') then
            if (rd_en1='1') then
              if (wr_en1='0') then
                if (counter1 /=0) then
                d_out<=Ram1(conv_integer(rd_addr));
                counter1<= counter1 -1;
                flag <='0';
               else --Ram1 is empty
                wr_en1 <='1';
                wait for 10 ns;
                rd_en1<= '0';
                wait for 10 ns;
                wr_en2 <='0';
                wait for 10 ns;
                rd_en2<='1';
                wait for 10 ns;
                counter1 <=0;
              end if;
            end if;
          elsif (rd_en2='1') then
            if(wr_en2='0') then
              if(counter2 /=0)then
                if (flag /='1')then
                  d_out<=Ram2(conv_integer(rd_addr));
                  counter2<= counter2 -1;
                else --Ram2 is empty
                  rd_en2<= '0';
                  wait for 10 ns;
                  wr_en2<= '1';
                  wait for 10 ns;
                  wr_en1<= '0';
                  wait for 10 ns;
                  rd_en1<= '1';
                  wait for 10 ns;
                  counter2 <=0;
                end if;
              end if;
            end if;
          end if;
        end if;
        wait on rd_clk,rd_en1,wr_en1,counter1,rd_en2,wr_en2,counter2;
        end process ;
        
         write:process is
         begin
         if(wr_clk'event and wr_clk='1')then
              if(wr_en1='1')then
                  if(rd_en1='0')then
                       if(counter1 /=16) then
                             Ram1(conv_integer(wr_addr))<= d_in;
                             counter1<=counter1+1;
                       else --Ram1 is full
                          wr_en1 <='0';
                          wait for 10 ns;
                          rd_en1<='1';
                          wait for 10 ns;
                          wr_en2<='1';
                          wait for 10 ns;
                          rd_en2<='0';
                          wait for 10 ns;
                          counter1<=16;
                          wait for 10 ns;
                       end if;
                  end if;
 
              elsif(wr_en2='1')then
                   if(rd_en2='0')then
                       if(counter2 /=16)then
                           Ram2(conve_integer(wr_addr))<=d_in;
                           counter2<=counter2+1;
                       else --Ram2 is full
                          wr_en2 <='0';
                          wait for 10 ns;
                          rd_en2 <='1';
                          wait for 10 ns;
                          wr_en1 <='1';
                          wait for 10 ns;
                          rd_en1 <='0';
                          wait for 10 ns;
                          counter2<=16;
                          wait for 10 ns;
                       end if;
                   end if;
              end if;
         end if;
         wait on wr_clk,wr_en1,rd_en1,counter1,wr_en2,rd_en2,counter2;
         end process ;
           
           fullempty:process is
           begin
           
           if(rd_en2='1' and wr_en1='1')then
              if(counter1=16 and counter2 /=0) then
                 full<='1';
              end if;
           elsif(rd_en1='1' and wr_en2='1')then
                if(counter1 /=0 and counter2=16)then
                  full<='1';
                end if;
           elsif (rd_en2='1' and wr_en1='1' )then
                if( counter1 /=16 and counter2=0) then
                    empty<= '1';
                end if;
           elsif(rd_en1='1' and wr_en2 ='1') then
               if(counter1=0 and counter2 /=16) then
               empty <='1';
               end if;
           end if;
          wait ;
      end process fullempty;
  end architecture;
    
    configuration conection of DualBuffer is
      for struct
          for Ram1,Ram2:Ram
             use entity work.Dual_Port_Ram(behavior);
           end for;
         end for ;
     end configuration conection ;
 

I think you need to go back to the basics of VHDL. This code follows no templates and will never produce a functioning design.

WHy have you used inout? Inouts are only really meant for tri-state drivers. If you read it and then write to it you get contention on the line, hence why you need a resolved type (like std_logic) to fix when one side drives '1' and the other size drives '0' (hence you get 'X'). The bit type will only accept 1 driver, meaning it has to be either in or out, not inout.
 

I'm studying at the University of Vhdl only for 1 semester
It is my practice, and I'll fix it, but I do not know how much
Thanks for the tips
what a bout this??
this is another program
in this program i use + function(sum of two bit_vectors) in package of numeric_bit_unsigned but my program cant use this package
i serch in internet and i found budy of this function but it is dose not work why?
can you help me?
sorry i know littel english
errors :

* Error: (vcom-11) Could not find ieee.numeric_bit_unsigned.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/serial/serial.vhd(5): (vcom-1195) Cannot find expanded name "ieee.numeric_bit_unsigned".
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/serial/serial.vhd(5): Unknown expanded name.
-- Loading package numeric_bit
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/serial/serial.vhd(9): VHDL Compiler exiting
my code :
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit_unsigned.all;
use ieee.numeric_bit.all;


package test is
 subtype byte is bit_vector(0 to 7 );
 end package;

entity serial is
  port (d_in:in work.test.byte;
        clock : in bit);
  end entity;
  
  architecture behavior of serial is
  
  signal cksum1:work.test.byte:=x"00";
  signal cksum :work.test.byte:=x"00";
  signal correct:work.test.byte:=x"00";
  type ram_array is array (natural range <>) of work.test.byte;
  function "+" (L, R : BIT_VECTOR) return BIT_VECTOR is
  begin
    return BIT_VECTOR(UNSIGNED(L) + UNSIGNED(R));
  end function "+";
  
  begin
    process is
      variable index_range: integer:=0;
      begin
         loop
           if (d_in =x"55") then
             wait on clock ;
             index_range :=conv_integer(d_in);
             variable ram:ram_array(index_range -4);
             for i in ram'range loop
               wait on clock;
               ram(i)<= d_in;
               cksum1<= "+"(cksum1,d_in);
             end loop;
             wait on clock;
             cksum<=d_in;
             if (cksum =cksum1)then
               correct<=x"AF";
           else 
             wait on clock;
         end loop;
       end process;
     end architecture;
 

several issues again. The main one is that numeric_bit and numeric_bit_unsigned are part of the VHDL2008 standard, and probably not included in ISE yet. You'll have to download the VHDL 1993 compatible versions from www.vhdl.org.uk/fphdl and add them manually to your project.

second, if you are going to include these packages, you dont need to define your own version of +, because numeric_bit_unsigned will already define it. also, when you've used it you've called it like a function, but because it is +, the L and R stand for Left and right, so you call it like:

cksum1 <= cksum1 + d_in;

thrid, this code will also not synthesise , so you cannot compile it in ISE anyway because:
1. You have used an infinite loop
2. you used lots of waits that are not synthesisable.
3. a for loop;


This code makes me think yoiu're a software guy trying to write VHDL. I suggest you stop writing VHDL now and get out a pen an paper. Now draw the circuit you want. Only when you've got a circuit should you write VHDL. HDL stands for Hardware Description language. It is not a programming language, it is a decription language. So if you dont know the circuit, how do you expect to decsribe it in VHDL?
 

hello
it become better?
i Separate processes and i use wait in my processes.
becuse in my processes , i give signals value ,i must use resolve sigals then i use std_logic or std_logic vector
but i recived this errors
what i must do?
i know littel vhdl and this is my exercise please hepl me

errors:
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(49): Cannot resolve indexed name as type ieee.std_logic_1164.std_logic_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(68): Cannot resolve indexed name as type ieee.std_logic_1164.std_logic_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(94): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(94): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(113): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(113): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(155): VHDL Compiler exiting


my code:

lib
Code: 
rary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
  

entity DualBuffer is
  port(d_in : in std_logic_vector(0 to 7);
        d_out: out std_logic_vector(0 to 7);
        wr_addr:in natural range 1 to 16;
        rd_addr:in natural range 1 to 16;
        wr_clk :in std_logic;
        rd_clk :in std_logic);
  end entity ;
  
  architecture struct of DualBuffer is
    signal empty,full :bit;
    signal counter1,counter2 :std_logic_vector(0 to 3):="0000";
    signal flag : bit:='1';
    signal wr_en1:std_logic;
    signal wr_en2:std_logic;
    signal rd_en1:std_logic;
    signal rd_en2:std_logic;
    
  
    component Ram is
      port( d_in :in std_logic_vector(0 to 7);
        d_out :out std_logic_vector(0 to 7);
        wr_clk,rd_clk :in std_logic ;
        wr_en,rd_en:in std_logic;
        wr_addr:in natural range 1 to 16;
        rd_addr :in natural range 1 to 16);
      end component Ram;
      
      begin
        Ram1 : component Ram
        port map (d_in =>d_in,d_out=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        Ram2 :component Ram
        port map (d_in =>d_in ,d_out=>d_out,wr_en=>wr_en2,rd_en=>rd_en2,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        read : process is
        begin
          if (rd_clk'event and rd_clk='1') then
            if (rd_en1='1') then
              if (wr_en1='0') then
                if (counter1 /="0000") then
                d_out<=Ram1(rd_addr);
                counter1<= counter1 -"0001";
                flag <='0';
               else --Ram1 is empty
                wr_en1 <='1';
                wait for 10 ns;
                rd_en1<= '0';
                wait for 10 ns;
                wr_en2 <='0';
                wait for 10 ns;
                rd_en2<='1';
                wait for 10 ns;
                counter1 <="0000";
              end if;
            end if;
          elsif (rd_en2='1') then
            if(wr_en2='0') then
              if(counter2 /="0000")then
                if (flag /='1')then
                  d_out<=Ram2(rd_addr);
                  counter2<= counter2 -"0001";
                else --Ram2 is empty
                  rd_en2<= '0';
                  wait for 10 ns;
                  wr_en2<= '1';
                  wait for 10 ns;
                  wr_en1<= '0';
                  wait for 10 ns;
                  rd_en1<= '1';
                  wait for 10 ns;
                  counter2 <="0000";
                end if;
              end if;
            end if;
          end if;
        end if;
        wait on rd_clk;
        end process ;
        
         write:process  is
         begin
         if(wr_clk'event and wr_clk='1')then
              if(wr_en1='1')then
                  if(rd_en1='0')then
                       if(counter1 /="1111") then
                             Ram1(wr_addr)<= d_in;
                             counter1<=counter1+"0001";
                       else --Ram1 is full
                          wr_en1 <='0';
                          wait for 10 ns;
                          rd_en1<='1';
                          wait for 10 ns;
                          wr_en2<='1';
                          wait for 10 ns;
                          rd_en2<='0';
                          wait for 10 ns;
                          counter1<="1111";
                          wait for 10 ns;
                       end if;
                  end if;
 
              elsif(wr_en2='1')then
                   if(rd_en2='0')then
                       if(counter2 /="1111")then
                           Ram2(wr_addr)<=d_in;
                           counter2<=counter2+"0001";
                       else --Ram2 is full
                          wr_en2 <='0';
                          wait for 10 ns;
                          rd_en2 <='1';
                          wait for 10 ns;
                          wr_en1 <='1';
                          wait for 10 ns;
                          rd_en1 <='0';
                          wait for 10 ns;
                          counter2<="1111";
                          wait for 10 ns;
                       end if;
                   end if;
              end if;
         end if;
         wait on wr_clk;
         end process ;
           
           fullempty:process is
           begin
           
           if(rd_en2='1' and wr_en1='1')then
              if(counter1="1111" and counter2 /="0000") then
                 full<='1';
              end if;
           elsif(rd_en1='1' and wr_en2='1')then
                if(counter1 /="0000" and counter2="1111")then
                  full<='1';
                end if;
           elsif (rd_en2='1' and wr_en1='1' )then
                if( counter1 /="1111" and counter2="0000") then
                    empty<= '1';
                end if;
           elsif(rd_en1='1' and wr_en2 ='1') then
               if(counter1="0000" and counter2 /="1111") then
               empty <='1';
               end if;
           end if;
          wait ;
      end process fullempty;
  end architecture;
    
    configuration conection of DualBuffer is
      for struct
          for Ram1,Ram2:Ram
             use entity work.Dual_Port_Ram(behavior);
           end for;
         end for ;
     end configuration conection ;

- - - Updated - - -


i can not add this part to my project.
i use this code
cksum<= cksum + d_in;
whith this function
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR(UNSIGNED(L) + UNSIGNED(R));
end function "+";
but it dose not work.
 

I told you before, you cannot convert a std_logic to an integer, it has to be a std_logic_vector.
Also, you cannot compile this code for an FPGA because of the wait statemnts and the multiple drivers.

To fix, remove the wait statemnts. Stop using inout.
 


sorry did you see my last code???
i dont use integer and bit vector
Gender of index for std_logic_vector is natural .is'nt it?
these errors are for this codes:

d_out<=Ram1(rd_addr);
d_out<=Ram2(rd_addr);
Ram1(wr_addr)<= d_in;
Ram2(wr_addr)<=d_in;


i Define d_out and d_in ,std_logic_vector
and i define rd_addr and wr_addr ,natural
and this is my component code for rams

component Ram is
port( d_in :in std_logic_vector(0 to 7);
d_out ut std_logic_vector(0 to 7);
wr_clk,rd_clk :in std_logic ;
wr_en,rd_en:in std_logic;
wr_addr:in natural range 1 to 16;
rd_addr :in natural range 1 to 16);
end component Ram;


every where i use std_logic_vector . is it wrong?
 

Ok sorry - no I didnt read because it looked the same.

YOu cannot access a component like that. What you're doing is trying to access an array, but you've maped a componented ram. You only need to mux the two ram outputs and select which one to use.

And why are the wait's still there?
 

You do not look too closely
please see it .
've worked very hard .
i use port map

Ram1 : component Ram
port map (d_in =>d_in,d_out=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);

Ram2 :component Ram
port map (d_in =>d_in ,d_out=>d_out,wr_en=>wr_en2,rd_en=>rd_en2,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);


i clean wait .is it correct??
please see it please
my code :
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
  

entity DualBuffer is
  port(d_in : in std_logic_vector(0 to 7);
        d_out: out std_logic_vector(0 to 7);
        wr_addr:in natural range 1 to 16;
        rd_addr:in natural range 1 to 16;
        wr_clk :in std_logic;
        rd_clk :in std_logic);
  end entity ;
  
  architecture struct of DualBuffer is
    signal empty,full :bit;
    signal counter1,counter2 :std_logic_vector(0 to 3):="0000";
    signal flag : bit:='1';
    signal wr_en1:std_logic;
    signal wr_en2:std_logic;
    signal rd_en1:std_logic;
    signal rd_en2:std_logic;
    
  
    component Ram is
      port( d_in :in std_logic_vector(0 to 7);
        d_out :out std_logic_vector(0 to 7);
        wr_clk,rd_clk :in std_logic ;
        wr_en,rd_en:in std_logic;
        wr_addr:in natural range 1 to 16;
        rd_addr :in natural range 1 to 16);
      end component Ram;
      
      begin
        Ram1 : component Ram
        port map (d_in =>d_in,d_out=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        Ram2 :component Ram
        port map (d_in =>d_in ,d_out=>d_out,wr_en=>wr_en2,rd_en=>rd_en2,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
        
        read : process (rd_clk) is
        begin
          if (rd_clk'event and rd_clk='1') then
            if (rd_en1='1') then
              if (wr_en1='0') then
                if (counter1 /="0000") then
                d_out<=Ram1(rd_addr);
                counter1<= counter1 -"0001";
                flag <='0';
               else --Ram1 is empty
                wr_en1 <='1';
                
                rd_en1<= '0';
                
                wr_en2 <='0';
                
                rd_en2<='1';
                
                counter1 <="0000";
              end if;
            end if;
          elsif (rd_en2='1') then
            if(wr_en2='0') then
              if(counter2 /="0000")then
                if (flag /='1')then
                  d_out<=Ram2(rd_addr);
                  counter2<= counter2 -"0001";
                else --Ram2 is empty
                  rd_en2<= '0';
                  
                  wr_en2<= '1';
                  
                  wr_en1<= '0';
                  
                  rd_en1<= '1';
                  
                  counter2 <="0000";
                end if;
              end if;
            end if;
          end if;
        end if;
        
        end process ;
        
         write:process(wr_clk) is
         begin
         if(wr_clk'event and wr_clk='1')then
              if(wr_en1='1')then
                  if(rd_en1='0')then
                       if(counter1 /="1111") then
                             Ram1(wr_addr)<= d_in;
                             counter1<=counter1+"0001";
                       else --Ram1 is full
                          wr_en1 <='0';
                          
                          rd_en1<='1';
                          
                          wr_en2<='1';
                          
                          rd_en2<='0';
                          
                          counter1<="1111";
                          
                       end if;
                  end if;
 
              elsif(wr_en2='1')then
                   if(rd_en2='0')then
                       if(counter2 /="1111")then
                           Ram2(wr_addr)<=d_in;
                           counter2<=counter2+"0001";
                       else --Ram2 is full
                          wr_en2 <='0';
                          
                          rd_en2 <='1';
                          
                          wr_en1 <='1';
                          
                          rd_en1 <='0';
                          
                          counter2<="1111";
                          
                       end if;
                   end if;
              end if;
         end if;
        
         end process ;
           
           fullempty:process is
           begin
           
           if(rd_en2='1' and wr_en1='1')then
              if(counter1="1111" and counter2 /="0000") then
                 full<='1';
              end if;
           elsif(rd_en1='1' and wr_en2='1')then
                if(counter1 /="0000" and counter2="1111")then
                  full<='1';
                end if;
           elsif (rd_en2='1' and wr_en1='1' )then
                if( counter1 /="1111" and counter2="0000") then
                    empty<= '1';
                end if;
           elsif(rd_en1='1' and wr_en2 ='1') then
               if(counter1="0000" and counter2 /="1111") then
               empty <='1';
               end if;
           end if;
          wait ;
      end process fullempty;
  end architecture;
    
    configuration conection of DualBuffer is
      for struct
          for Ram1,Ram2:Ram
             use entity work.Dual_Port_Ram(behavior);
           end for;
         end for ;
     end configuration conection ;
but i have same error yet
errors:

** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(49): Cannot resolve indexed name as type ieee.std_logic_1164.std_logic_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(68): Cannot resolve indexed name as type ieee.std_logic_1164.std_logic_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(94): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(94): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(113): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(113): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/test/buffer.vhd(155): VHDL Compiler exiting

- - - Updated - - -

in this exercise i must use component and configuretion.
i define a project for ram and in this project i want use Previous project.
i difine 2 projects in one folder.
 

a component is not an array. You can do what you want, but you have to do it differently:

1. Have a separate internal signal for the d_out of each ram
2. select which d_out you want to use.

You have connected d_out to both rams, therefore you have created contention. Ram1 is not a signal, so you cannot acccess it as if it was one. In your code, you are driving d_out from 3 sources - Ram1, Ram2 and the process.

I suggest you draw your circuit on paper.
 
Reactions: n.mehr

    N

    n.mehr

    Points: 2
    Helpful Answer Positive Rating
your means is i must define 2 d_out in my component?? like this
component Ram is
port( d_in :in std_logic_vector(0 to 7);
d_out1 ut std_logic_vector(0 to 7);
d_out2 ut std_logic_vector(0 to 7);
wr_clk,rd_clk :in std_logic ;
wr_en,rd_en:in std_logic;
wr_addr:in natural range 1 to 16;
rd_addr :in natural range 1 to 16);
end component Ram;

begin
Ram1 : component Ram
port map (d_in =>d_in,d_out1=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);

Ram2 :component Ram
port map (d_in =>d_in ,d_out2=>d_out,wr_en=>wr_en2,rd_en=>rd_en2,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);

well What should I do??

this is my code for project one which i use in project two . in project one i define ram and array for ram and in project to in part of configuration i refer to project one
my code:

Code: 
  library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Dual_Port_Ram is
  port (wr_ck : in std_ulogic;
  rd_ck : in std_ulogic ;
   wr_addr : in natural;
  rd_addr : in natural;
  d_out : out std_logic_vector(0 to 7);
   d_in : in std_logic_vector(0 to 7);
   wr_en,rd_en :in std_ulogic);
  end entity Dual_Port_Ram ;
  
  architecture behavior of Dual_Port_Ram is
    type memory_type is array (0 to 15) of std_logic_vector (7 downto 0) ;
    signal ram :memory_type ;
    
   
    begin
      write: process(wr_ck) is
      begin
        if wr_ck'event and wr_ck ='1' then
          if wr_en='1' then
            if (wr_addr /= rd_addr) then
              ram(wr_addr)<= d_in;
            end if;
          end if;
        end if ;
      end process write ;
      
      read: process (rd_ck) is
      begin
        if rd_ck'event and rd_ck='1' then
          if rd_en='1' then
            if (wr_addr /= rd_addr) then
              d_out <= ram(wr_addr);
            end if;
          end if;
        end if;
      end process read ;
    end architecture behavior ;

i realy thank you.you answer me and help me thank you
 

No Tricky means: use a multiplexer to select which ram d_out output gets assigned to d_out where you've instantiated the rams. What you've shown now is two outputs shorted together.
 

i can not underestand. errors are for this code:
d_out<=Ram1(rd_addr);
d_out<=Ram2(rd_addr);
Ram1(wr_addr)<= d_in;
Ram2(wr_addr)<=d_in;

what shold i do?
i have 2 process .in read process ,i want if Conditions are corect ,run this code ( d_out<=Ram1(rd_addr);
d_out<=Ram2(rd_addr); )
and in write process i want if conditions are corect , run this code ( Ram1(wr_addr)<= d_in;
Ram2(wr_addr)<=d_in; )

- - - Updated - - -

i have problem in my another project
i write a code for ram .it has 3 process.read and write and wave_gen.
in wave_gen , i value the signals like this

wave_genrocess is
variable t:time:= 10 ns;
variable p:time:=5 ns;
begin

wr_ck<= '1' ,'0' after t ,'1' after 2*t,'0' after 3*t, '1' after 4*t;
rd_ck<= '0' ,'1' after p,'0' after 4*p,'1' after 5*p,'0' after 6*p;
wr_en<= '0' ,'1' after 2*p, '0' after 4*p, '1' after 8*p,'0' after 9*p;
rd_en<= '1','0' after 5*p ,'1' after 2*p,'0' after 4*p, '1' after 7*p;
wr_addr<="0000","0001" after t,"0010" after 3*t;
rd_addr<= "0010", "0001" after p;

wait;
end process;
but i can not see wave .why?


please help me for all my Questions.
thank you

- - - Updated - - -

and in this project i have same problem why i see 00000000 in my correct port?
i must see another things
why dose not go enything in my ram ,in both program??
my code :
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity serial is
	port(
	     clk : in std_logic;
	     data_in : in std_logic_vector(7 downto 0);
	     correct : out std_logic_vector(7 downto 0):="00000000");
end entity;

architecture behavior of serial is
type state is (S0, S1, S2, S3);
type RAM_type is array (0 to 49) of std_logic_vector(7 downto 0);
signal RAM : RAM_type;
signal cnt,offset_addr,RAM_addr : integer range 0 to 49:=0;
signal data_sum : std_logic_vector(7 downto 0):=(others=>'0');
signal status :state;
signal num_of_byte :std_logic_vector (7 downto 0);
signal cksum :std_logic_vector (7 downto 0);

begin
process(clk)
begin
if(rising_edge(clk)) then
	case status is
		when S0 =>							
		   if (data_in = x"55") then
				status<=S1;	
				correct <= x"AF";
			else
				status<=S0;				
			end if;
		when S1 =>
			num_of_byte <= data_in;
			status<=S2;
			offset_addr <= RAM_addr+1;
			correct <= x"AF";
		when S2 =>
			if(cnt < num_of_byte) then
				RAM(cnt + offset_addr) <= data_in;
				RAM_addr <= cnt + offset_addr;
				data_sum <= data_sum + data_in;
				cnt<=cnt+1;
				correct <= x"AF";
				status<=S2;
			else
			  cksum <= data_in;
				if(data_sum = cksum) then
				correct <= x"AF";
				status<=S3;
				cnt<=0;
				end if;
			end if;
		when s3 =>
			if(data_in = x"AA") then
				 correct <= x"AF";
				status<=S1;
			end if;
	end case;	
end if;
end process;

end architecture;


I'm really need help
 

Please please please, I suggest that you

1. Draw your circuit on paper.
2. Read up more in a VHDL textbook or your notes, preferably one that uses digital logic examples.
3. Google VHDL multiplexor

THe problems you have are because you are treating the ram like and array. In that file, there is no array. You have made a component RAM, and instantiated it twice. Imagine RAM1 is one chip on a cictui board, and RAM2 is another chip. BOTH of them produce a data_out on separate wires, and you have to chose which wire to use. You cannot use both at the same time.

It looks like the waves are not forming because you stopped the code with a break point.

The data is stuck at "000000000" becuase it hasnt changed yet. You need to check the waveform to make sure the correct inputs have come in to change it.
 


thanks for all Guidance
I've solved some of the problems
 

i write a program it is compile.
i write 4 test bench for my program and all test bench are compite.
but i cant see any wave why??
please help me



this is error for test bench 1
see Bottom of Page

and this is my code for test bench 1
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test_bench_3 is
end entity;
--in test bench vase khata dar stop bit ast
architecture test3 of test_bench_3 is
    signal rxd: std_logic;
    signal rxck: std_logic;
    signal rxf: std_logic;
    signal error_for_bit: std_logic;
    signal error_for_stop:std_logic;
    signal error_for_parity: std_logic;
    
     begin 
        test3: entity work.reciver(behav)
           port map(rxd=>rxd,rxck=>rxck,rxf=>rxf,error_for_bit=>error_for_bit,error_for_stop=>error_for_stop,error_for_parity=>error_for_parity);
     
     
           wave_gen:process is
                begin
                  --inja stop bit bejye inke 1 bashe 0 ast kr ghalate
                  rxck<='1','0' after 10 ns,'1' after 20 ns,'0' after 30 ns,'1' after 40 ns,'0' after 50 ns,'1' after 60 ns,'0' after 70 ns,'1' after 80 ns ,'0' after 90 ns,'1' after 100 ns,'0' after 110 ns,'1' after 120 ns,'0' after 130 ns,'1' after 140 ns,'0' after 150 ns,'1' after 160 ns,'0' after 170 ns,'1' after 180 ns;
                  rxd<='0','1' after 15 ns ,'1' after 35 ns ,'1' after 55 ns,'1' after 40 ns,'1' after 75 ns,'1' after 95 ns,'1' after 115 ns,'1' after 135 ns,'1' after 155 ns ,'0' after 175 ns;
                  wait;
        end process;
            
    end architecture;

this is piture of error for test bench 2
see Bottom of Page

and this is my code for test bench 2
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test_bench_2 is
end entity;
--in test bench vase khata dar parity ast
architecture test2 of test_bench_2 is
    signal rxd: std_logic;
    signal rxck: std_logic;
    signal rxf: std_logic;
    signal error_for_bit: std_logic;
    signal error_for_stop:std_logic;
    signal error_for_parity: std_logic;
    
     begin 
        test2: entity work.reciver(behav)
           port map(rxd=>rxd,rxck=>rxck,rxf=>rxf,error_for_bit=>error_for_bit,error_for_stop=>error_for_stop,error_for_parity=>error_for_parity);
     
     
           wave_gen:process is
                begin
                  rxck<='1','0' after 10 ns,'1' after 20 ns,'0' after 30 ns,'1' after 40 ns,'0' after 50 ns,'1' after 60 ns,'0' after 70 ns,
                  '1' after 80 ns ,'0' after 90 ns,'1' after 100 ns,'0' after 110 ns,'1' after 120 ns,'0' after 130 ns,
                  '1' after 140 ns,'0' after 150 ns,'1' after 160 ns,'0' after 170 ns,'1' after 180 ns;
                  --dar inja man data dadam be rxd
                  --parity az inja ghalat ast
                  --data ba parity ghlat man=01111111101
                  rxd<='0','1' after 15 ns ,'1' after 35 ns ,'1' after 55 ns,'1' after 40 ns,'1' after 75 ns,'1' after 95 ns,
                  '1' after 115 ns,'1' after 135 ns,'0' after 155 ns ,'1' after 175 ns;
                   wait;
        end process;
            
    end architecture;
 

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