Help me in Current steering DAC

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amahi07

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Please help in providing some Document for current or resistive DAC .
Iam facing some problem in settling time , INL , DNL .

My DNL range is -1 to 1
My INL range is -1.5 to 1.5

But Iam getting very large INL , but DNL is not giving any problem .
 

The currents steering DAC is easy get good DNL, if you want get good INL:
first, calculate the current cell's output resistance, the finite output resistance is a large error source effect the INL.
second: The mismatch between the current cells. Calculate the matching error,(reference the foundry's device matching form).
About the resistive DAC, it cann't get high speed but can get high output swing. when you design resistive DAC, take care the switch's parasitic resistor and capacitor, when you use segment resistors DAC.
You can reference the book "CMOS data converters for communications "
 
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