I am a newbie in Analog IC design. Please help to create a test bench for measure the PSSR of my Two Stage OTA in cadence. Some resources, someone applied AC analysis to measure te PSSSR on the other hand someone used XF noise analysis. Please can anyone help to me for the standard methods.
There are no standard designs and no std. PSRR methods yet PSRR is reported in dB referred to changes in input/supply.
The best way is to give a spectral plot PSRR for each supply rail in dB with the transfer function from supply to input. The current sources and mirror topology greatly affects PSRR and Gain Bandwidth of the compensation filters will ultimately reduce the error a finite amount.
For example the 741 used only Vcc supplied current sources so Vee was 99% of the PSRR error in split supplies.
While error increases from gain reduction from rising f ,so too does Zout which may affect load regulation error.
Here you can adjust the frequency of ripple on Vcc & Vee while choosing 0 to my chosen max AC ripple on both or either. With Vpp monitors scattered around.
Notice the error from Vee ripple is the derivative of the applied noise signal.
Since the ratio is referred to input and is reduced by forward gain [dB], then PSRR may reduce by twice the increase in gain [dB]? CORRECTIONS BELOW
e.g. if an Op Amp has unity gain with a PSRR of 80 dB and rejection reduces with forward gain, supply noise out then increases by Av² or twice in [dB]
Upon closer examination, the above was disproved by measurements in the simulation using the 741 internal model in Falstad's simulation.
The supply noise does not affect the input stage as much as the final stages, so when PSRR is referenced to input levels by the closed loop gain, it was found that output supply ripple was linear with Av, closed loop voltage gain.
Far more significant effects on high Av gain on the 741 was Vio, the input offset voltage which have trim ports to Vee supply. Although not simulated on Falstad, which uses almost perfectly trimmed transistors, There is a -271 uV, Vio input offset simulated and a trimmable DC voltage source on the input to null the output. Vio and Ii the input bias current times the input R imbalance were significant sources of DC output offset voltage in the 741 during the '70's and today there are far better designs for this characteristic.
Today the 741 is still used as a teaching device and still works and is very inexpensive to reproduce without all the laser trimming used in many modern IC's but there are still much better choices.
More corrections For example the 741 used only Vcc supplied current sources so Vee was 99% of the PSRR error in split supplies.
The above is true, so beware of test conditions when reading specs for PSRR. Some may show single ended vs differential with only 3 dB difference but still not show difference in V- vs V+ PSRR.
This was also simulated and found that in the 741 the Vcc positive collector supply has almost 60 dB better PSRR than the Vee PSRR which makes that suited for single supply. A noisy charge pump Vcc inverter for Vee must be evaluated for output noise in high gain situations.
i.e. if both supplies had equal ripple from a dual SMPS, 99.9% of the supply ripple on the output after gain or referred to input like unity gain will come from th Vee negative supply due to how the current source biases are referenced. However some modern Op. Amps (OA's) may have corrected or improved this aspect. So linear regulators are still commonly used in noise critical applications.