Help me Fpga hardware problem

[aminr11]

I have write a serial simple program to communicate with pc , i have synthesis is with xilinx isp and also synthesis it , and simulate it well,but on my hardware cpld xc9500 series with 108 macrocells ,it program well on also verify but,when i look on my ocsope i can't see anything on it.my clock connected to one of the i/o pin 75 ,and it's help me to generate my desired baud rate. i really confuse ,i'm really freak out,some one take my hand, plz someone help me,i assure about my program.what's problem? could it be the time constraint ?i really get confuse. HELPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPp,,,,,,HELLLLLLLLLLLLLPPPPPPPPPPPPPP

 

[s3034585]

hi first check whether ur logic is getting the clock or not. and check the constraint file. wether the pins what u are looking at on the oscil... are connected to the output of ur program or not...

also try to trace the signals which are used to assign the output that u r expecting....

 

[prajit]

Please check the Power Lines and also confirm the clock signal.
Check the ground connections