Help me fix code as the clko isn't brought to outside

I have a problem when I synthesize the code below; I get it synthesized but I the Libero toolchain (yes I use ACTEL FPGA's) doesn't bring the clko to outside so I can't asign a pin to it in designer...

Synthesize

Because you are driving one variable in two processes, this must be error, try this

process(clk, a, b, reset)
variable var_temp: std_logic_vector(1 downto 0);
begin
var_temp := a & b;
if reset = 'o' then
temp := (others => '0');
elsif(clk = '1' and clk'event) then
case var_temp
when "10" =>
temp := temp + 1;
when "01" =>
temp := temp -1;
when other => null;
end case;
end if;
end process;


good lack

Re: Synthesize

mobile-it said:

I have a problem when I synthesize the code below; I get it synthesized but I the Libero toolchain (yes I use ACTEL FPGA's) doesn't bring the clko to outside so I can't asign a pin to it in designer...

Code:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity ledcounter is
generic(
        datawidth: positive :=8
        );
port (clko: in std_logic;
        a: in std_logic;
		b: in std_logic;
        c:    out std_logic_vector(datawidth-1 downto 0)
        );
end ledcounter;

architecture code of ledcounter is
signal temp :std_logic_vector(datawidth-1 downto 0);

begin

process(clko)

begin

if(a='1' and rising_edge(clko)) then
temp<=temp+1;
end if;

if(b='1' and rising_edge(clko)) then
temp<=temp-1;
end if;

end process;

c<=temp;
end code;

Click to expand...

hello friend U just do small modifications like the following in ur code it will work perfectly as u wished it to work.

Added after 46 seconds:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity ledcounter is
generic(
datawidth: positive :=8
);
port (clko: in std_logic;
a: in std_logic;
b: in std_logic;
c: out std_logic_vector(datawidth-1 downto 0)
);
end ledcounter;

architecture code of ledcounter is
signal temp :std_logic_vector(datawidth-1 downto 0);

begin

process(clko,a,b)

begin
if rising_edge(clko)then
if(a='1') then
temp<=temp+1;

elsif(b='1') then
temp<=temp-1;
end if;
end if;

end process;

c<=temp;
end code;

Re: Synthesize

Thank you very much guys I think everything is working at this time. The only problem at this time that is happening on my board is that when I push one of the switches on I have some noise entering my FPGA so I have to search a solution for this.

Re: Synthesize

always put all used signals in the sensitivity list

Added after 2 minutes:

I think you need to make debouncing to debounce the switches