mobile-it
Advanced Member level 1
I have a problem when I synthesize the code below; I get it synthesized but I the Libero toolchain (yes I use ACTEL FPGA's) doesn't bring the clko to outside so I can't asign a pin to it in designer...
Code:
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity ledcounter is
generic(
datawidth: positive :=8
);
port (clko: in std_logic;
a: in std_logic;
b: in std_logic;
c: out std_logic_vector(datawidth-1 downto 0)
);
end ledcounter;
architecture code of ledcounter is
signal temp :std_logic_vector(datawidth-1 downto 0);
begin
process(clko)
begin
if(a='1' and rising_edge(clko)) then
temp<=temp+1;
end if;
if(b='1' and rising_edge(clko)) then
temp<=temp-1;
end if;
end process;
c<=temp;
end code;