Hi Guys:
In designing a silicided poly PGS, I face with this error " The CMOS1 contact process is designed to contact silicided Island or Poly only. It is not designed to make connection to unsilicided Island or Poly". Hence if I design a poly overlapped with silicide bloack layer to form the PGS, with X shaped Metal1 and contact PGS ground, I have this Poly+Silicide block overlapping with the Metal1+contact, how do I really design the silicided poly PGS in compliance with this error. Thanks in advance
Rgds