Help me design a CMOS Voltage Limiter

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Ipanema

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Hi, this is my first post here. Hope to learn from you all.

I need to design a high speed (Gbps) CMOS voltage limiter, which can limit output swing to 1.65~2.475V all the time in 3.3V process. Pls help. TQ.
 

Re: CMOS Voltage Limiter

Try using limiting amplifier stages, which are basically cascaded version of differential amplifiers


Rgds
 

Re: CMOS Voltage Limiter

Hi, thanks for your reply.
The LA that I know of only consists of cascaded diff amp. It will limit the lower swing if NMOS diff pair is used, but how can I gurantee the swing (upper and lower limit) and offset across temperature and process variation? Pls let me know which LA architecture that ur talking about or even better if you could provide me with the circuit as well.
I have in mind of using some sort of voltage clipping circuitry, but have failed to implement thus far. Any advice?

Thanks
 

CMOS Voltage Limiter

LVDS has similar specs. to your design. In LVDS Tx, it contains CMFB and just a regular OP-Amp. However, to maintain a stable common mode voltage, the effort has been made to the digital side, i.e., trying to keep the cross point of D+/D- as stable as possible.
 

Re: CMOS Voltage Limiter

HI, thanks for your reply. You are right about maintaining the common mode point with CMFB, but the swing will also vary together with the common mode point when CMFB try to adjust the tail biasing. Just a thought from your advice, can we combine the advantage of LA(limit swing) + LVDS/CMFB (constant common mode) = constant swing and common mode ? How to do this? Any advice?

Thanks.
 

Re: CMOS Voltage Limiter

Hi, BTW do you mean digital D+/D- as the LVDS input?
 

Re: CMOS Voltage Limiter

Ipanema said:
Hi, BTW do you mean digital D+/D- as the LVDS input?
Click to expand...

Actually LVDS TX only needs single-ended logic inputs. What I mean is converting the single-ended logic into a symmetrical true-/complement-singal pair, which is still digital, so that the complexity of line driver (OP-Amp indeed) can be reduced.

Also, CMFB circuit may need to adjust head/tail currents of the OP-Amp altogether. The OP-Amp simply consists of differential stages and head/tail current sources. Simple OP-Amp, right?
 

Re: CMOS Voltage Limiter

Hi Thanks for your reply. I can get a good differential input to the LVDS driver. Can you pls show me your schematic for the LVDS driver? By having two tails (upper and lower tail), will it clip the voltage swing while maintaining the common mode level with CMFB?

Thanks.
 

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