Help me design a 3x frequency multipler

[camel_RF]

Hi,

I am interested in designing a 3X frequency multiplier with below spec:
Freq in = 1.2 GHz
Freq out = 3.6 GHz
Outpur power = ~ 20dBm
Used at FR4 board

I have no experience for the design.
Anyone can help me on this?

 

[sergio mariotti]

pin diode odd multiplier

The preferred multiplication factors are 2, 4, 8 etc. because you can use a diode rectifier. It's know that the rectifier produce a a pulsating out freq that is twice the input.

To design a tripler you should take in account the following tips:
1) drive a BJT or FET, or diode (a comb diode is better) with sufficently large power.
2) build a output circuit that tune the 3rd harmonic.
3) The input circuit is critic. It should be a bandpass for the fundamental but shoul reflect the 3rd harmonic. Some one reflect the 3rd harm. by a short someother by an open.
Because the multiplication efficency is low (-10 to -20 dB) an output amplifier is required to get enough power output.

Remember that a X3 is inerenthly narrower than a X2 or a X4.

 

[activewei]

1.2ghz bpf schematic

I would suggest you to design with Step recovery diode. The required input driving power is relative low and therefore the efficiency is higher. to get 20dBm of output power, it is necessary to add an amplifier after the multiplier (common practice)

 

[lguancho]

frequency multipler

Hi, some years ago, I designed a passive x3 multiplier at 1.2Ghz (what a coincidence!), using antiparallel diode. I based my design on an old HP application notes. Just go to agilent website, and you should be able to get the paper.

Inherently, antiparallel diodes pair have some even production suppression. You need some filtering after the multiplier. Disadvantage: no conversion gain. It is simple to design

 

[camel_RF]

antiparallel schottky diode frequency multiplier

Hi lguancho,

Might I have the title for the HP application note?
Is it possible for you to share your schematic diagram to me?
Thanks in advance.

 

[pewang]

fet multiplier circuit

I would suggest you to design with Step recovery diode. The required input driving power is relative low and therefore the efficiency is higher. to get 20dBm of output power, it is necessary to add an amplifier after the multiplier (common practice)

The step recovery diode design is very suitable for high frequency design.But for camel_RF design requirement,a FET multipler is ok enough.tTune the output match circuit to 3rd harmonic and input match to fundmental.additional gain stage is required.AWR Microwave Office have a such example,its design note is below.
FET Multiplier

This project demonstrates how to set up MWO for the nonlinear simulation of a FET frequency doubler. Also, it demonstrates some of the new capability found in v6, such as using the tuner to control the display of pre-simulated data. The tuner is also employed in the same fashion that previous versions of MWO employed, namely to tune element parameters through defined states using equations and variables. The tuner is a very powerful tool allowing complex simulations to be brought under the control of the designer, and refined.

Overview
This multiplier uses a single transistor whose bias is fixed at just below the specified pinch off voltage of the channel; this ensures that the device produces an output waveform that has a fairly strong second harmonic content. Other arrangements are possible, such as combining two transistors in anti-phase, but for the purposes of this example project one transistor is used. With this simulation two parameters are being used to explore the circuit behavior, namely frequency and drive power. The drive frequency is defined using the individual options for each schematic. With MWO v6 all circuits (linear, nonlinear and EM) own their own frequency ranges. Right click on 'FET Frequency Multiplier' in the Circuit Schematics browser and select the options in the menu. Here, one will see the frequency list used to define the simulation frequency set. To define the drive level, an equation has been placed in the schematic that sets up the range of power values. A complimentary equation defines a variable (Power) that is indexed to the list of potential powers used in the simulation. In this example, the list of power levels is defined by the statement ‘PowerStates = stepped(9,13,0.5)’.

DC and Dynamic IV
The instantaneous voltage at the device terminals is plotted along with the DC static IV curves. These serve to give some insight into the device behavior under these extreme drive conditions. As a check on the bias conditions, edit the schematic 'FET Frequency Multiplier' and substitute the number -20 in place of the variable in the power parameter for the input port. Re-simulate and the quiescent operating point will be seen. The schematic 'FET DC IV Tests' is used for the simulation of the DC IV curves of the transistor.

Output Spectrum
To assist the designer in seeing the actual drive frequency and the frequency of the associated second harmonic, markers have been added to the traces of the fundamental and second harmonics. The markers will update whilst the tuner is being used giving instant feedback as to the drive frequency. To see the marker snap to the trace, after each movement of the tuner control release the mouse button before moving the tuner control to the next position.

Waveforms
The time domain plot of the multiplication process can readily be seen when comparing the drive waveform and the load waveform. Use the tuner to vary either the drive level or select the drive frequency simulation results.


Tuning
The dynamic IV measurement (IVDLL) makes use of the new tune feature of v6. This new feature allows the designer to select a pre-simulated trace using the tuner. In this project, the IVDLL is calculated for all the frequencies associated with the project, the tuner allows the display of a single trace.

The bitmap below illustrates how the measurement dialog is used to use the tuner to select a specific simulation result.

 

[lguancho]

3x frequency multiplier

Hi, the exact agilent application note is:

AN1054: Low cost frequency multiplier using SMT PIN Diodes.

Just go to www.agilent.com, do a search for AN1054, you should get it easily!

Inside this article, a X5 and X3 multiplier designs are discussed. The X3 design works at 1.8GHz, no issue for you to adapt it to 1.2GHz.

The PIN diode is HSMP-3822 from agilent. Any equivalent parts should be OK.

If you need 20dBm output, you need to add a medium power amplifier after the multiplier.

 

[nandopg]

freq multipler

Frequency multipliers using diodes work fine, but it is very hard to get good output level flatness over frequency. Also the output power in this multipliers changes significantly over temperature, meaning that a lot of circuitry would be need in order to stabilize its output.
If only positive power supply is an issue in your design, FETs would demand the use of a voltage inverter (with all problems relative to EMI) to generate the bias gate. If this is the case that doesn't look like to be a good approach.
Low noise bipolar transistors use only positive voltage and can be used effectively as the active nonlinear device in frequency multipliers.
A valid approach to design frequency multipliers with bipolar transistors can be outlined as:
1- Choose a transistor with gain greater than 1 at the desirable frequency.
2- Apply negative voltage and current feedback to the transistor aiming flat gain and good input and output return loss over the frequency band ranging from the fundamental up to the harmonic of interest.
3- Adjust the bias level and driver to optimize odd or even harmonics, depending the case. If you have a nonlinear simulator this situation can be easily simulated if not do it experimentally.
This approach has the following advantages:
1- The multiplier doesn't require any tuning in production time.
2- It supplies an output level at the harmonic flat over a broad percent bandwidth.
3- The circuit is very stable over a broad temperature range.
4- As the output return loss is adjusted through the negative feedback to a value that, in practice, range 8 to 15dB, the mismatching introduced by the multiplier output onto the harmonic bandpass filter is minimum, guarantying this way the output level flatness.
The disadvantage of this approach is its inherently low efficiency.
I have been using this approach very successfully in several situations.

NandoPG

 

[lguancho]

step recovery s band frequency multiplier

I must emphasize that the PIN diode is a low cost approach, and you can get the design up very fast (1/2 a day or less, depend on how good is your prototyping skill). Matching is minimal if you look at diode impedance with a VNA (quite well match).

I used it to generate a fixed LO for my radar exciter module, so flatness is not my concern. With the harmonics separated by 1.2GHz, you can easily design a low section count BPF to filter away the undesired harmonic.

 

[camel_RF]

surface mount x5 frequency multiplier

Hi NandoPG,

I am interested to know how do I choose a Low Noise Transistor?
Would you possible to outline in more details of this design especially on the negative voltage and current feedback?
Any reference/application note for me to understand more on this approach?

Thanks in advance.

 

[activewei]

bjt frequency tripler

nandopg: I am also interested to try out your proposal. Do upload some application notes related to your design or your actual design implemented (if it is fine for you)...

 

[alucard]

passive frequency multiplier tripler

i'm in the midst of designing a x2 multipier. Was wondering if anyone of you have success in simulating the ckt behavoiur in ADS or other CAD. Please advice on the diode model used.

Thanks!

 

[biff44]

waveform plot + mwo

A X3 is no more difficult than a X2 multiplier when using diodes. You just have to configure the diodes differently to accentuate odd order currents rather than even order currents. There are PLENTY of commercial applications of X3 multipliers to 40 GHz that are in production today. One approach:

https://www.wenzel.com/documents/2diomult.html
Also a series antiparallel pair generates 3rd order harmonics. These types of diodes multipliers are not as efficient, as they use resistive schottky diodes.

A FET multiplier is good for X3. You might want to have series connected LC circuits at the output to return the fundamental and X2 currents to ground.

A SRD approach is a good one if you want a high efficiency. You also need to use some series connected LC circuits at the output to supress fundamental and X2 currents, and to yield the output waveshape that is rich in X3 content.

 

[springf2000]

jfet frequency multiplier schematic

HSMP3822 is good and chep way,it is eay to get this frequency Mutiplex