Help me decide on a version of backend flow

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sudhirtj

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Backend flow

Hi All,

I want to know which flow is better?

a. Gate_level_Netlist -> Floorplan -> scan_chain_insertion -> place -> spare_cell_insertion -> CTS

b. Gate_level_netlist -> Floorplan -> Place -> spare_cell_insertion -> scan_chain_insertion -> CTS

Keeping in mind for
Gate_level_netlist - Design Compiler
Floorplan - First Encounter
Scan chain insertion - Physical Compiler
Placement - Physical Compiler
Spare cell insertion - Physical Compiler
Scan chain reordering - First Encounter (if required)
CTS - First Encounter

All comments are welcome.

Thanks,
Sudhir
 

Re: Backend flow

this document maybe usefull to you
it explain backend flow.
 

Re: Backend flow

If you take a First Encounter Tutorial, you will see the example of a typical flow.
I would recommend you to use magma, if you have access to it. If not try to keep you flow simple. Btw I have seen the request for the spare parts in different chips, but I have never seen that they were really used.
 

Re: Backend flow

Hi Honeyxyb,

I am not able to see any documents. Can you please attach?

Also, moorhuhn I am looking for a generalised flow and not the tool flow. In the generalised flow, i want to put the tool which i specified.

-Sudhir
 

Re: Backend flow

hi :

I think you can get " TSMC Reference Flow Release 5.0 " from tsmc .

it can help you !
 

Re: Backend flow

I don't think any of your design flow is good for you.
I think you should learn about P&R.
And more, you must know that the inserting scan chain is done by DFT before you P&R.
 

Re: Backend flow

I'd prefer the following flow, without spare_cell_insertion:

Gate_level_Netlist -> Floorplan -> place -> scan_chain_insertion -> CTS

Based on my experience, spare cells will not be used. Also you should insert scan_chain after Floorplan and Placement, because any changes in placement of components affect the scan chains.

Regards,
KH
 

Backend flow

spare gate is very useful when front end need change at very late stage before tapeout, and metal fix. for very big design, it will cost a big money if you do full tapeout. with spare gate, you need only to change metal layer.
if you design is not big, not difficult, and you have prove you design in FPGA. maybe spare gate is not necessary.
you can insert scan chain before P&R, and do scan chain reorder after P&R, so the place would not be touched.
there is no fix flow, tool is changing fast. once proved flow maybe not good for next generation desing.
 

Re: Backend flow

Hi khorram,

you are true and i have taken up that flow
Gate_level_Netlist -> Floorplan -> place -> scan_chain_insertion -> CTS

With this flow, i can avoid scan reordering step and thereby avoiding some amount of time in the flow.

Hi horzonbluz,

In the current situation, where the trend is much of integration, you will have to do from synthesis to gds, you should be in a position to chose your design flow. you have to insert the scan, you have to insert the spare and you have to do synthesis and P&R for your blocks.

-Sudhir

Added after 3 minutes:

Hi simonhcc,

Is the TSMC Reference flow 5.0 free for download. I dont have login for the ecaonline of TSMC. Can anybody, send me the TSMC Reference flow 5.0

Thanks,
Sudhir
 

Re: Backend flow

Is the TSMC Reference flow 5.0 free for download.
Click to expand...
Here it is.

Regards,
Kh

/Deleted.
**broken link removed**
(klug)/
 

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