Help me change a code to achieve a dynamic reconfigurability

[deepa]

this is a simple multiplexer code of a 8*1 mux,using 4*1 muxes.how can i change this to acheive dynamic reconfigurability..please help me in this topic


module mux8_to_1(i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2,o) ;
input i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2;
output o;
reg o;
reg mux_out1,mux_out2;
MUX4_to_1 m1(i0,i1,i2,i3,s0,s1,mux_out1);
MUX4_to_1 m2(i4,i5,i6,i7,s0,s1,mux_out2);
mux2_to_1 m3(mux_out1,mux_out2,s2,o);
// ### Please start your Verilog code here ###
endmodule

module MUX4_to_1(i0,i1,i2,i3,s0,s1,o) ;


// ### Please start your Verilog code here ###
input i0,i1,i2,i3;
output o;
input s0,s1;
wire d0,d1,d2,d3;
wire o;

assign d0=~s0&~s1&i0;
assign d1=~s0&s1&i1;
assign d2=s0&~s1&i2;
assign d3=s0&s1&i3;
assign o=d0|d1|d2|d3;
endmodule


module mux2_to_1(i0,i1,s,o) ;
input i0,i1,s;
output o;
wire o;
assign o=(i0&~s)|(i1&s);

// ### Please start your Verilog code here ###
endmodule

 

[jarodz]

Re: reconfigurable codes

For your reference.

module mux
(
IN,
SEL,
OUT
);

parameter       SEL_BITS = 4;

input   [(1<<SEL_BITS)-1:0]     IN;
input   [SEL_BITS-1:0]          SEL;
output                          OUT;

integer                         ii;

reg                             OUT;
always @(IN or SEL)
begin
        for(ii = 0; ii < 1<<SEL_BITS; ii = ii + 1)
        begin
                if(SEL == ii)
                        OUT = IN[ii];
        end
end

endmodule

Sincerely,
Jarod