Help me build a System Verilog verification environment

[ankit12345]

Im using VCS_mx 7.1.2

need to built systemverilog verification env.

I think.......VCS is not supporting all the SV constructs.........

How to start...how to proceed........

Is there any example with full env.....like FIFO.....for reference................

If so,Where can i get that???

Give me some ideas.......

I have experience in verification using verilog.......

But SV verification incudes lot of high level verilfication concepts......
....like fun coverage....assertions....constraints....

I think i can start FIFO SV env using asic-world examples........
which is built in e(SPECMAN)
https://www.asic-world.com/examples/specman/fifo.html

Coz.....most of the SV and e constructs are similar ..........for FIFO(my module is simillar to FIFO,so i wannna give a try on FIFO)

https://www.asic-world.com/examples/systemverilog/memory.html
Please go through the above link.......and tell me where is the test case in that example.....

Fallowing the books......
SV for verification---chris spear
Art of verification using SVA----Faisal Haque
SV lrm

Added after 14 minutes:

In h**p://www.asic-world.com/examples/specman/fifo.html
example...........

show me how to write a simple test case....
I got some idea...still some confusion.........

 

[aji_vlsi]

warning interface not instantiated

Ankit,

Im using VCS_mx 7.1.2

Almost 3 years old version, why not try lagtest 2006.06, it supports lots and lots of SV/VMM now.

need to built systemverilog verification env.

I think.......VCS is not supporting all the SV constructs.........

Update the version first!

Is there any example with full env.....like FIFO.....for reference................

If so,Where can i get that???

Look in SNUG 2006, we have a paper on exactly that - VMMing a testbench with FIFO as an example.

And of-course if you get our book, Pragmatic approach to VMM adoption, that has FIFO and a Serial-to-parallel converter (also some Ethernet broadcast etc.) All examples are designed ground up to guide you through the steps.

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[ankit12345]

System verilog----

Dear ajeetha,

Thanks for the guidence.
I got the SNUG paper,going through it.

VCS 7.2,7.1.1,7.2.1 ........these are the versions available.....
which is the best one out of the above for SV.....
else I will talk to my system admin regarding this.....

Regards
Ankit

 

[aji_vlsi]

Re: System verilog----

Dear ajeetha,

Thanks for the guidence.
I got the SNUG paper,going through it.

VCS 7.2,7.1.1,7.2.1 ........these are the versions available.....
which is the best one out of the above for SV.....

Usually the latest, as far as I know there is 2006.06-10 or something. I use that at my company. Check with vcs_support.

Ajeetha, CVC
www.noveldv.com

 

[vinod_cheedella]

Re: System verilog----

hi ankit,

try vcs 2006-06 version, it supports most of the SV features, constraints and many more which are very helpful for verification environment.

better try to check with your administrator regarding the latest version of vcs available.

anyways, please let me know what features do u need to build a complete verification environment...

 

[ankit12345]

System verilog----

Got vcs 2006-06.started working on it.


I have knowledge of specman.

I have gone through the various tutorials on SV.

getting ideas how to use constraints,assertions,coverage,struct ......coz these are available in specman.........
not able to think interms of systemverilog..............

how to build an env in SV for fifo(not exactly fifo,my module is simillar to fifo,so i cant use predefined queue of SV)
WE can do write,read,remove,shuffel.....etc on my module...

not able to think interms of SV........

i wrote tasks............for each operation
each task when called.......will force the input of dut.........
in test cases......the order of tasks(ex: read,write,read,write)
will verify the required functionality.

other way of building verification env is.......
in specman,order of sequencess will verifi the required funcationality for this module........

should i build env,where the test cases are done by calling tasks????
then I think ,constraints are not much useful for this module
should i write using input sruct???where the input is initally random...........then constraint it to test the specfic functionality????

is there any other way to build env????

I wrote taskes and assertions in SV for this module.
Got strucked after this........give me some idea........

I think.............calling tasks ............is silly..........which will not use much of the feauters of SV.

thenks in ADVANCE
ankit

 

[aji_vlsi]

Re: System verilog----

Ankit,
I'm glad that you are asking the right set of questions.

Got vcs 2006-06.started working on it.



I think.............calling tasks ............is silly..........which will not use much of the feauters of SV.

thenks in ADVANCE
ankit

This is 100% well said! This is really where a methodology comes in handy. If you are OK, I can work with you to turn your Specman example to a nice SV/VMM based one and we can publish it together. Please let me know if you would like to pursue it.

Regards
Ajeetha, CVC
www.noveldv.com

 

[ankit12345]

System verilog----

When using verilog for verification,
to store data like ethernet packets,which requires lot of memory.......
We use C to store these packets.......

Do i need to do the same when we are building the env in SV??
objects are created dynamic in SV,they can be deallocated.

Which is better???to store in SV r C????

Added after 46 minutes:

I think VCS2006-06 is not supporting 'rand' construct........


then how can i do random checking???
any other way??????

 

[aji_vlsi]

Re: System verilog----

Do i need to do the same when we are building the env in SV??
objects are created dynamic in SV,they can be deallocated.

Use SV's dynamic array, queues, assoc array.

Which is better???to store in SV r C????

I would go with SV as it is one language.

I think VCS2006-06 is not supporting 'rand' construct........

Of course it does. Did you look at our example SNUG code etc? We use it all the time. Show us a piece of code that doesn't work. Maybe inside module it didn't work? Show us code to comment better.

then how can i do random checking???
any other way??????

Improper terminology -- "rand" gives you random generation, not "checking", checking is something you need to build it on your own.

HTH
Ajeetha, CVC
www.noveldv.com

 

[ankit12345]

System verilog----

Dear anitha,
where can i get information about the constructs which are supported by my tool???

I got a SVlrm with my VCS tool.........u can find it in /VCS_HOME/docs/userguide..
what is this about????why some comments are written "construct not implimented"
next to rand----its written "construct not implimented"
so ithought its not yet implimented.

let me try and check weather the tool is supporting r not.....

"random cheching".....my english is poor......
I mean random verification.......I got what u said.....

thanks

Added after 2 minutes:

I mailed to ur gmail ID........please reply ASAP.

 

[mssajwan]

Re: System verilog----

Hi ankit,
at /doc/userguide/ location of ur synopsys tool u can get svtb.pdf
or even you can download it from net. just check at google.
one more thing this tutorial will tell u about the support VCS has for SV.

-regards
-Manmohan

 

[ankit12345]

System verilog----

USING VCS

Error-[UTOPN] Unknown type or port name
The type name 'clocking' is unknown, or the identifier 'cb' has not been
listed as a port, or the declaration might represent an instance
missing parentheses.
"proj.sv", 18: token is '@'
clocking new @(posedge clk);

what mistake i did??? help me

 

[aji_vlsi]

Re: System verilog----

USING VCS

Error-[UTOPN] Unknown type or port name
The type name 'clocking' is unknown, or the identifier 'cb' has not been
listed as a port, or the declaration might represent an instance
missing parentheses.
"proj.sv", 18: token is '@'
clocking new @(posedge clk);

what mistake i did??? help me

Show us full code. Also try contacting vcs_support - in any case you need to share full code.

Ajeetha, CVC
www.noveldv.com

 

[ankit12345]

System verilog----

interface proj(input bit clk);
logic [1] grant, request;
logic reset;

clocking new @(posedge clk);
output request;
input grant;
endclocking

modport test (clocking new,
output reset);

modport dut (input request, reset, clk,
output grant);


endinterface

Added after 2 minutes:

vcs -sverilog -debug_all proj.sv

 

[aji_vlsi]

Re: System verilog----

Ankit,
Few issues in your code:

new is a keyword in SV, so change it to say "cblk_new"

 logic [1] grant, request; 
 
What does the [1] buy you here? It is incorrect syntax I believe. Use:

 logic grant, request;

You would very likely get "interface not instantiated" error at the end as you are not using this interface anywhere.

Ajeetha, CVC
www.noveldv.com

 

[vinod_cheedella]

Re: System verilog----

vcs-2006-06 version supports constraints "randomize" i think so,
by defualt they work in program scope....

 

[ankit12345]

System verilog----

I want to creat a packet using class.
Simillar to this.

class Packet
rand int header;
rand int len;
rand byte payload[];
int crc;
rand bit goodcrc;
constraint G { len > 1; payload.size == len ; }
function void post_randomize;
if (goodcrc)
crc = payload.sum;
else
crc = 0;
endfunction
endclass

when sending the packet by packing............
packet p = new;

packedpacket = {<<byte{p}};

then goodcrc is also getting packed.
Im not interested in sending this bit goodcrc feild.

one solution is to use
packedpacket = {<<byte{p.header, p.len--------------

any other solution????
Im not interested to pack all the feilds of class.
can i declare these uninterested feilds out of class???
any probs????how to do that????
any other idea?????


In specman,this bit goodcrc is called virtual feild.
rest of the interested feilds are called physical feild.
when we pack,only physical feilds are packed.virtual feilds are neglected.

thanks in advanced

 

[vinod_cheedella]

Re: ** SYSTEM VERILOG **

hi Ankith,

declare this unwanted variable "goodcrc" outside the class scope, lets say in program scope. ok, now in the post_randomize() function do randomize this goodcrc like
goodcrc=$random, and remaining things are as before..

class methods can see the signals which are outside the class also, because the class declaration and the goodcrc declaration are both at the same level, so it will work...

the only difference is goodcrc=$random is inheritant with p.randomize() in your test case, and now i just make it as explicit here.

Now, the object "p" does't having goodcrs, though the functionality is one and the same....

bye
vinod

 

[aji_vlsi]

Re: System verilog----

Ankit,
You are looking for E's Physical field equivalent - simply put, no, it doesn't exist in SV. Only way is to write your own "pack" function. This is where methodology comes in - so that you don't realize this after trial and error. For instance VMM demands/requires that user writes a "byte_pack" and "byt_unpack" functions (virtual) for every transaction class. IIRC AVM also has this named "Packetizer/Depacketizer".

Good Luck
Ajeetha, CVC
www.noveldv.com