Help me buffer & distribute clock signal in Virtex II de

[voho]

Design virtex II pro

Hi All,


I want to buffering, and distributing clock signals in a Virtex II pro.
I intend to connect the clock input to the BREFCLK . :?:

Some ideas, and you can add any you have.

regards

 

[yerics]

Design virtex II pro

I think it's Ok ,
just add a IBUFGDS and BUFG after IOB
I am just using in this manner

 

[voho]

Re: Design virtex II pro

Hi yerics,



One comment for your design Xilinx has verified RocketIO operation with a reference clock (REFCLK) frequency of 125 MHz (2.5 Gbps serial) and 156.25 MHz (3.125 Gbps serial) using the following oscillators: :idea:



:arrow: Epson EG-2121CA:
http://www.eea.epson.com/go/product...Id=EEA.QD.Crystal_Oscillators.2_5VOscillators

:arrow: Pletronics LV1145B:
http://www.pletronics.com/LV1100B.htm

Regards

 

[voho]

Re: Design virtex II pro

Hi,

to minimize jitter, REFCLK should be routed through an IBUFG only.

regards

 

[yerics]

Design virtex II pro

I use differiential clock signal to input FPGA
so i use IBUGDS to distribute clock to ROCKETI/O
and use a BUFG to distribute clock to other logic part.
I think Xilinx only gives reference oscillators
not must use them

 

[speedoak]

Re: Design virtex II pro

hi,guys:
Do you plan to use V2pro PowerPC405 core??I want to use it to work as a signalling packet processing, not datapath packet, but I feel nervous to use it. any successful implementation of it??

 

[yerics]

Design virtex II pro

I AM EVALUATING POWERPC 405 CORE IN XILINX VERTEXII PRO.
WE HAVE A PLAN TO MOVE OUR ORIGINAL BOARD PROCESS INTO IT.