longqingshan
Newbie level 6
![Newbie level 6](/styles/images/ranks/blevel3.gif)
I have a doubt about ESD protection system showed in FIG.
There are two ESD current flow paths in PS and ND mode.
For instance, for PS mode, the ESD current can flow through DP to VDD, and then through power clamp to VSS. The ESD current can also directly flow through MN’s parasitical NPN transistor to VSS;
What I want to make sure is which path will triggered in reality?
And how to layout the ESD MOS, guard ring?
There are two ESD current flow paths in PS and ND mode.
For instance, for PS mode, the ESD current can flow through DP to VDD, and then through power clamp to VSS. The ESD current can also directly flow through MN’s parasitical NPN transistor to VSS;
What I want to make sure is which path will triggered in reality?
And how to layout the ESD MOS, guard ring?