Help me about cadence ldv v3.0!

ncverilog $recordvars $dumpon

When I run it , I can't add any signals to waveform window.
Operate following:
a:1. Run the "Affirma launch tool".
2. Select the "Verilog","Verilog-Xl Desktop","Graphical" to creat a session.
3. Add a verilog file "Test.v" and select it.
4. Click the "VerilogXL Desktop" button to run the Verilog-XL.
5. Select the signals ,and press the right button ot pop-up the menu.
6. Click the "Wave trace". appear a message ""No such file or direct- WeiLong_288" and nothing in waveform window.
b:1.execute:verilog +gui Test.v.
2. Select the signals ,and press the right button ot pop-up the menu.
3. Click the "Wave trace". appear a message ""No such file or direct- WeiLong_288" and nothing in waveform window.

The licence is for ldv v3.3 . I think it isn't matcing or I have not right set it.
Who have the licence for ldv v3.0, Pleace follow a copy to me,I Will treatly appreciate your timely help.

For LDV 3.0:


CENSORED

Thank you very much!

to sbot:
I'll apply it at once

the probleme as of old.

Dear sbob:
Thank you for your timely help!
I apply the license, but appear the same problem. Can you tell me how I set the license, the platform is windows 2000.

Hi Long Yan,

You should set the environment variable LM_LICENSE_FILE to point to the location of the license file I posted earlier. Maybe you have another problem. The verilog-xl simulator would not start if you had licensing problems. Are you a new user of verilog simulators? After reading your initial post again I am wondering if you are creating a dump file with your test.v simulation. Maybe you could post your test.v code.

Thanks,
sbob

Hi Long Yan,

Have you tried using ncverilog and signalscan? These are also included in LDV 3.0 and I find them much better than using verilog-xl (verilog +gui).

sbob

Hi sbob,
Thank you very much!
I'm a IC logic design engineer, and have 2 years experience. I once designed a 16-bit dsp and a 32-bit cpu.
I work in front-end, the design tools include modelsim, fpga complier etc. Ihaven't applied the verilog-xl or ncverilog. I want learn it and apply it afterward. In the area, I'm a beginner! So I hope get your help.


If the train project's source code is following, Please tell me how I modify and simulate it in verilog-xl.

module Tain_Adder_8 ();

reg [ 7:0] A,B;
reg ci;
wire [ 7:0] D;
wire Co;

assign {Co,D} = {1'b0,A} + {1'b0,B} + {1'b0,Ci};

always
# 10 {A,B,Ci} <= $random;

endmodule

I normally only use the tool in command-line mode, but usually, you need to include some kind of compiler directive to signal it to dump a file. Usually, I use something like this:

initial
begin
$shm_open("Sim");
$shm_probe("AC");
...
$shm_close;
end

in some cases, you can use the $recordvars directive, but i think that directive is not supported on windows.
strut911

Oh! thanks, I'll try it

Thanks for your help!

Hi,

The following will also generate the dump file for all signals in you're design:


initial begin
$dumpfile("test.dmp");
$dumpvars;
$dumpon;
end

sbob

Hi,

The following will also generate the dump file for all signals in you're design:


initial begin
$dumpfile("test.dmp");
$dumpvars;
$dumpon;
end

sbob

Hello,
If you run ldv on Windows, you only click to /waves.shm/waves.trn to open waveform, and if you run ldv on Linux you can type "signalscan&" and view waveform.
And then the LDV4.0 is the best for Window and LDV5.0 is the best for Linux
Vinh

verify your .sinenv , rewrite variable swave = $path/swave.

hello all,
do you have LDV5.0 lic***s*e file for Linux
thanks

I May try. Later , send it to u. can U send a template for linix?