Help JFET Transistor Biasing? Particularly Drain Resistor

Hey everyone,

I have been running some simulations of JFETs in order to study a bit about how to bias JFETs properly and also to teach myself along the way. I'm having problem with some of my calculations though. I am currently able to accurately calculate the operating point of a simple JFET circuit so long as it only has a source resistor. However, I've noticed that as soon as the drain resistor gets large enough to limit the current to be lower than the expected current draw for some source resitor and Idss value, then the operating point of the transistor becomes elusive and strange to me and I'm unable to calculate it. I feel that it has something to do with changes in drain-source voltage drop (maybe gate-source too?) but I can't figure out exactly how to calculate it accurately.

Similarly, I am confused as to how to bias a JFET well enough as to basically negate the differences between individual components - similar to how you can by using a voltage divider bias network for a BJT.

Help?

commathe said:

... However, I've noticed that as soon as the drain resistor gets large enough to limit the current to be lower than the expected current draw .........

Click to expand...

It is NOT the task of the drain resistor RD to "limit" the current. The transistor acts as a current source and the current is determined by VGS. RD is necessary for producing the output voltage.

Interesting. I definitely need to review how I've been looking at things, but I'm also slightly more confused now. How is a JFET able to create current? Can you use it as a source of power? I had always thought of it as drawing the current from the battery.

commathe said:

Interesting. I definitely need to review how I've been looking at things, but I'm also slightly more confused now. How is a JFET able to create current? Can you use it as a source of power? I had always thought of it as drawing the current from the battery.

Click to expand...

No - of course, the JFET cannot "create" a current and it is no source of power.
However, if it is operated in it´s active region it behaves like a (non-ideal) current source.
The current source analogy can be explained as follows:
The current Id depends only very little on the applied voltage VDS. Primarily, Id is determined by Vgs.
Therefore, the inclusion of a resistor Rd does not alter (or only to a small amount) the current Id.
However, a minimum value for Vds is necessary to bring (or to keep) the JFET into this active region.

Thanks! That really helps this self taught noob. I guess i misunderstood the meaning of current source. I'm still confused about why im getting these results when RD is too large but I guessit must be getting into the linear region.

commathe said:

Thanks! That really helps this self taught noob. I guess i misunderstood the meaning of current source. I'm still confused about why im getting these results when RD is too large but I guessit must be getting into the linear region.

Click to expand...

Yes - when Rd is too large the current Id develops a large voltage across Rd causing a reduction of Vds (across the JFET) below the active limit (because the supply Vcc is fixed).
As another visualization you can imagine the D-S path as a very large resistor Rds in series with a small or mid-valued resistor Rd - both connected between Vcc and ground.
In this case, the current depends only very little on Rd and is primarily determined by the large value of Rds. That means: Vcc in conjunction with Rds can be regarded as a (non-ideal) current source.
And the value of Rds is controlled by Vgs.

If a Jfet is a linear amplifier then it is never operated at IDSS. IDSS is when it is turned on as hard as it can go with a gate-source bias voltage of zero.
A source resistor is usually used to provide some negative feedback to reduce the wide range of spec's.

An example is a 2N3819 Jfet that has an IDSS ranging from 2mA to 20mA. Without a source resistor then some will be turned on hard, some will be linear and some will be cutoff if they are all biased the same.

A P-channel Fet is a current source (it sources a constant current to the load from the positive power supply voltage).
An N-channel Fet is a current sink (it sinks current through the load to ground).