I'm a beginner.When I complie this VHDL file of my IC design homework, I encounter with the error. I have searched many forums and know the reasons now. But I don't know how to make it right. If anyone can help me, I really appreciate. At last, thank you.
I'm a beginner.When I complie this VHDL file of my IC design homework, I encounter with the error. I have searched many forums and know the reasons now. But I don't know how to make it right. If anyone can help me, I really appreciate. At last, thank you.
A ripple counter uses the output of one flip-flop as clock for the next stage. As a result, each stage gets an additional delay related to the preceeding and and the output bits toggle at different times. This causes glitches in the decoded output and limits the maximum counter frequency.
A synchronous counter uses the same clock for all flip-flops and more complex logic for the D input of each flip-flop. It's the preferred way to design a counter in programmable logic or ASIC.
It's easy to write a synchronous counter in VHDL
Code:
signal p: unsigned[2 downto 0];
...
process (clk)
if clk'event and clk='1' then
p<=p + 1;
end if;
end process;
Another comment on the design. The state "1000" is only transient and can be omitted as well as p3. A binary counter will count from "111" to "000" without additional logic.