help in verilog hdl codes problems

[hareshcooleng]

i was writing down my up/down counter program. but now i design adder to connect its input to the output of counter so any on know about how to i do it. any code about its.

 

[jducluzeau]

What you want is to connect the outputs of one module to the inputs to another module?
For example :
-updown is the name of your up/down counter.
-adder your adder
-top is the top module where updown and adder are two submodule instantiated

module top

input ....
output ...

updown counter1(inputs_counter,outputs_counter);


...
endmodule

 

[aasharaaj]

Pl provide with the full code for the same.