Help in understanding comparing read/write cycle times in SRAM versus "DDR SDRAM"

[FlyingDutch]

Hello,

for some time I am trying to compare the shortest (obtainable) times of read/write cycles for particular SRAM and "DDR SDRAM" ICs. I am asking thgis question in context of two FPGA boards: one with static SRAM memory chip on-board and second with "DDR3L SDRAM" on-board. The first model of FPGA board is "Cmod A7" with Artix-7 FPGA and 512 K x 8 -bit SRAM ( ISSI IS61WV5128BLL-10BLI SRAM chip). hera are links to board description and SRAM chip datashet:

https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start

https://www.issi.com/WW/pdf/61-64WV...10.2033698690.1605360817-432973477.1602934204

The second model of FPGA board is "QMTECH Xilinx Artix-7" with 256 MB of DDR3 RAM. Here is links to bard description and DDR3 SDRAM chip:

https://pl.aliexpress.com/item/4000...chweb0_0,searchweb201602_4,searchweb201603_55

https://pl.mouser.com/datasheet/2/671/2Gb_1_35V_DDR3L-1283747.pdf

I can understand SRAM datasheet, but datasheet of DDR3 SDRAM datasheet is confusing for me. Could someone to explain how to properly delinate possible shortest times ( in nano-seconds) of read/write cycle and how to compare them to adequate times of SRAM memory.

Thanks in advance and regards

 

[FvM]

DDR RAM is very effective when accessing data in bursts or better whole data pages, but ineffective in single address access. For read access, you have to await at least the CL (CAS latency) delay printed on the first datasheet page. After that, you get a new data value with auto address increement every half clock cycle.

 

[FlyingDutch]

DDR RAM is very effective when accessing data in bursts or better whole data pages, but ineffective in single address access. For read access, you have to await at least the CL (CAS latency) delay printed on the first datasheet page. After that, you get a new data value with auto address increement every half clock cycle.

Hello @FvM,

as far as I understood your correctly it is 10 ns (SRAM) versus 13.91 ns (DDR3)? If yes using DDR RAM chips seems to be more profitable. Only advantage for using static RAM chips seems to be for me simpler controller.

Best Regards

 

[ads-ee]

The advantage of SRAM is not just the simpler controller it is the predictable latency of the device, the device latency never changes no matter where you read or write to the device. DDR3 may need to be refreshed, you need to start another transfer if you exceed the row/column boundaries in a burst, random accesses to single addresses will severely impact the memory performance.

Hence the reason modern computer systems use DDR# RAM for main memory storage, but have different layers of SRAM cache inside the processors for fast storage that has minimal latency.