Help in minimizing macrocells in a Altera, in VHDL

[btminzon]

HI people. I have a code that count pulses of clock, and put the exit high or low (like a pwm, but user enters the number os pulses on high and the number of pulses on low). I have available a Altera 3064, and i need also divide clock per 8, before counting. After compilation and synthesis, the code are using (with Quartus 6.0) 68 macrocells, and the 3064 has just 64. Any one can help me, how to change this code in a better one? thanks everybody

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ErosaoSS is
port (
Dados: in std_logic_vector(10 downto 0);
Clock: in std_logic;
Start: in std_logic;
Receber: in std_logic_vector (1 downto 0);
Saida_pulso: out std_logic
);
end ErosaoSS;

architecture ErosaoSS_arch of ErosaoSS is

signal tempo_ton: integer range 0 to 900 := 0;
signal tempo_toff: integer range 0 to 900 := 0;
signal TON: std_logic_vector (10 downto 0);
signal TOFF: std_logic_vector (10 downto 0);
signal contador: std_logic_vector(3 downto 0) := "0000";
signal clock_out: std_logic;

begin

divide_clock: process (clock,Start)
begin
if Start = '0' then
contador <= (others => '0');
clock_out <= '0';
else if (clock 'event and clock = '1') then
if (contador <= 8) then
contador <= contador + 1;
else
contador <= (others => '0');
clock_out <= not clock_out;
end if;
end if;
end if;
end process;

escolhe: process(receber,dados,start)
begin
if (Start = '0') then
if (Receber = "01") then
TON <= dados;
else if (Receber = "10") then
TOFF <= dados;
end if;
end if;
end if;
end process;


pulsa_ton: process (Start, clock,TON,TOFF)
begin
if (Start = '1') then
if (clock 'event and clock = '1') then
if (tempo_ton < TON) then
tempo_ton <= tempo_ton + 1;
saida_pulso <= '1';
else if (tempo_ton = TON) then
tempo_toff <= 0;
tempo_ton <= tempo_ton + 1 ;
else if (tempo_toff < TOFF) then
tempo_toff <= tempo_toff + 1;
saida_pulso <= '0';
else if (tempo_toff = TOFF) then
tempo_ton <= 0;
end if;
end if;
end if;
end if;
end if;
else if (Start = '0' or Start = 'Z') then
saida_pulso <= '0';
end if;
end if;
end process;

end ErosaoSS_arch;

 

[smilermd]

Try the next clock divider, it should help.

divide_clock: process (clock,Start)
begin
if Start = '0' then
contador <= (others => '0');
else if (clock 'event and clock = '1') then
contador <= contador + 1;
end if;
end process;

clk_out <= contador(2);

 

[btminzon]

dear smilermd, that's why i like forums, thanks your help. It's so much fast doing like this. I tried too, succesfully, change all std_logic_vector by integer range 0 to 16, and this, minimize 4 macrocells. And i don't know why. Do you have idea why VHDL synthetysis is better with integer instead of std_logic_vector? anyway, thanks again!!!

 

[smilermd]

Help in minimizing macrocells in a @ltera, in VHDL

You're welcome.
I don't know why integers are better than STD_LOGIC_VECTOR, may be this depends on vhdl synthetiser or on device.