Help in @ltera max epm7128slc84-15

chip: epm7128slc84-15
software: maxplus2
program: vhdl

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY golf00 IS
PORT (a1, a2,a3, a4,a5, a6,a7, a8,a9, a10,a11, a12,a13, a14,a15: IN std_ulogic;
a16,a17,a18,a19,a20,a21,a22, a23,a24, a25,a26, a27,a28, a29: IN std_ulogic;
a30,a31,a32,a33,a34,a35,a36,a37,a38,a39,a40,a41,a42,a43,a44,a45,a46,a47,a48: IN std_ulogic;
res, cp : IN std_ulogic;
q : OUT std_ulogic;

qa : OUT std_ulogic_vector(6 downto 0)

);
END golf00;

ARCHITECTURE RTL OF golf00 IS



signal temp1: std_ulogic_vector(9 downto 0);
signal temp2: std_ulogic_vector(9 downto 0);
signal temp3: std_ulogic_vector(9 downto 0);
signal temp4: std_ulogic_vector(9 downto 0);
signal temp5: std_ulogic_vector(9 downto 0);
signal temp6: std_ulogic_vector(9 downto 0);
signal temp7: std_ulogic_vector(9 downto 0);

signal temp8: std_ulogic_vector(3 downto 0);
signal temp9: std_ulogic_vector(3 downto 0);
signal temp10: std_ulogic_vector(2 downto 0);
signal y1,y6: std_logic;
signal y2,y5: std_logic;
signal y3,y4: std_logic;


BEGIN
y1<= a1 and a2 and a3 and a4 and a5 and a6 and a7 and a8 and a9;
y2<=a10 and a11 and a12 and a13 and a14 and a15 and a16 and a17 and a18 and a19;
y4<=a20 and a21 and a22 and a23 and a24 and a25 and a26 and a27 and a28 and a29;
y5<=a30 and a31 and a32 and a33 and a34 and a35 and a36 and a37 and a38 and a39;
y6<=a40 and a41 and a42 and a43 and a44 and a45 and a46 and a47 and a48;

y3<=y1 and y2 and y4 and y5 and y6;


TEMP1<=a9&a8&a7&a6&a5&a4&a3&a2&a1&'1';
TEMP2<=a19&a18&a17&a16&a15&a14&a13&a12&a11&a10;
TEMP3<=a29&a28&a27&a26&a25&a24&a23&a22&a21&a20;
TEMP4<=a39&a38&a37&a36&a35&a34&a33&a32&a31&a30;
TEMP6<='1'&a48&a47&a46&a45&a44&a43&a42&a41&a40;

TEMP9<=y6&y4&y3&y2;
PROCESS(Y3)
BEGIN
if(Y3'EVENT AND Y3='0') THEN
TEMP5<=temp1 and temp2 and temp3 and temp4 and temp6;
END IF;
END PROCESS;
qa(0)<=not(temp5(1) and temp5(3) and temp5(5) and temp5(7) and temp5(9) );
qa(1)<=not(temp5(2) and temp5(3) and temp5(6) and temp5(7) );
qa(2)<=not(temp5(4) and temp5(5) and temp5(6) and temp5(7) );
qa(3)<=not(temp5( 8 ) and temp5(9) ) ;

PROCESS(Y3)
BEGIN
if(Y3'EVENT AND Y3='0') THEN
case temp9 is
WHEN"0111"=>TEMP10<="100"; --40
WHEN"1011"=>TEMP10<="011"; --30
WHEN"1101"=>TEMP10<="010"; --20
WHEN"1110"=>TEMP10<="001"; --10
WHEN OTHERS=>TEMP10<="000";--00
END CASE;
END IF;
END PROCESS;
qa(4)<=TEMP10(0);
qa(5)<=TEMP10(1);
qa(6)<=TEMP10(2);
q<=y3;

END RTL;

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output : it is wrong.
if i change the chip like flex6000(epf6010atc100), it is ok.
i want to use epm7128slc , why not?
plese help me!!

Hello nbastar,

Could you explain in more detail what is going wrong? Does your simulation fails? Or does the synthesis fails? …


Bye,
cube007

I suggest to verify the number of pin, I beleave you are using somes pin not
able for your job.
To many input????, do not assign pin, and compile using normal compilations and put
optimozation in space and not in time, follow the error messages of compiler
regards
M

hello cube007

the simulation is failed.
the detail follows:

Error: No partition possible because logic cell q requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell qa6 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell qa5 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell qa4 requres too many[48/36] inputs from PIA

Error: No partition possible because logic cell temp59 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp58 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp57 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp56 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp55 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp54 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp53 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp52 requres too many[48/36] inputs from PIA
Error: No partition possible because logic cell temp51 requres too many[48/36] inputs from PIA

Error: No fit found,generating Report file

Error: Logic cell 'q' requires too many[48/46]inputs from PIA
Error: Logic cell 'qa4' requires too many[48/46]inputs from PIA
Error: Logic cell 'qa5' requires too many[48/46]inputs from PIA
Error: Logic cell 'qa6' requires too many[48/46]inputs from PIA
Error: Logic cell ':110' requires too many[48/46]inputs from PIA
Error: Logic cell ':111' requires too many[48/46]inputs from PIA
Error: Logic cell ':112' requires too many[48/46]inputs from PIA
Error: Logic cell ':113' requires too many[48/46]inputs from PIA
Error: Logic cell ':114' requires too many[48/46]inputs from PIA
Error: Logic cell ':115' requires too many[48/46]inputs from PIA
Error: Logic cell ':116' requires too many[48/46]inputs from PIA
Error: Logic cell ':117' requires too many[48/46]inputs from PIA
Error: Logic cell ':118' requires too many[48/46]inputs from PIA

hello cube007

i get it . just i choose " multi-Level synthesis for max3000/5000/7000 Devices" in max plus2.
But i don't real understand it .
Does this let me use the all lab like lab A,lab B,lab C etc . right ?or wrong?

regard
nbastar