reyge
Member level 4
What are the verilog coding considerations when getting signals outside of an FPGA board?
I am implementing a code that gets an input signal either inside or outside of the FPGA (actually coming also from another FPGA board). So the user can choose whether to have an internal or external input. However, when the external input is chosen, the output becomes different... I assume that the external connection is ok... I have put buffers on the input and i think i have a fully synchronous design.. what else could i possibly be missing?
thanks a lot!
I am implementing a code that gets an input signal either inside or outside of the FPGA (actually coming also from another FPGA board). So the user can choose whether to have an internal or external input. However, when the external input is chosen, the output becomes different... I assume that the external connection is ok... I have put buffers on the input and i think i have a fully synchronous design.. what else could i possibly be missing?
thanks a lot!