help in correcting verilog code

[Manuv16589]

hi there,
I am writing parallel adder using task. But i am getting error in code.The code is as follows

module demo(x,y, cin, s,cout);
parameter N=3;
    input [N:0]x,y;
    input cin;
    output [N:0]s;
	 output cout;
	 reg cout;
	 reg [N:0]s;
	 reg [N+1:0]c;
	 integer i;
	 always@(x,y,cin)
	 begin
	 c[0]=cin;
	 for(i=0;i<=N;i=i+1)
	 faddr(c[i+1],s[i],x[i],y[i],c[i]);
	 cout<=c[N+1];
	 end
task faddr;
input a,b,cin;
output s,cout;
begin
		s=a^b^cin;
		cout=(a&b)|(b&cin)|(cin&a);
end
endtask

endmodule

The error is "ERROR:HDLCompilers:159 - "demo.v" line 35: Illegal argument passed to port 4 (output) of task 'faddr' ". what is this error? Please solve this problem. Thanks in advance.

 

[FvM]

The error complains about y passed as output argument s of the task. y is an input and can't be assigned as output.

Do you know, that the arguments are assigned by order?

 

[Manuv16589]

The error complains about y passed as output argument s of the task. y is an input and can't be assigned as output.

Do you know, that the arguments are assigned by order?

thanks for the reply.
I think i have passed the arguments correctly. I have passed y for b. Isnt it correct?

 

[manojkhandelwal]

first pass inputs in order and then outputs...not the other way around...you have passed y for s, and not b;
the argument order for your case should be x,y,c and then s,c[i+1]...

 

[Manuv16589]

Yeah thanks...it worked