adedia.
Sorry for being a bit 'short' with you. Sometimes I get frustrated when I spend time explaining something that doesn't need to be explained.
COme On...Show Up your idea sir, Would you please draw it. ( Hope i asked well and correct)
...You see, now I feel guilty. You did indeed ask correctly
So here it is.
I think *some* explaination is probably needed, I'll try and keep it brief.
Right, the two inputs to the circuit are 'DATA IN' and 'CLOCK' and the only real output is 'DATA OUT'. Points *A* are all connected, as are points *B*.
The data input goes through an AND gate. When the other input to this gate (DATA_EN) is low, only 0's are inputed, and your data is ignored, giving us the 'four 0's after data'. The CRC encoder also has an enable line (CRC ENABLE), which, when '1' will allow the encoder to do its job, when '0' the encoder simply behaves like a standard shift register. The 4-bit counter is used to provide these controls, it also switches the MUX, so you can send your data, then the CRC checksum straight afterwards automatically. The top box 'Shift register' is simply a 4-bit delay.
Here's what should happen (haven't tested it yet):
After the first 4 clock's, the first 4 bits are in the shift register, and the CRC encoder is doing its job (CRC_ENABLE = 1, DATA_EN = 1). The next clock will send out the first bit of your data from the shift-register to the 'DATA OUT' because the MUX is switched to that.
After 8 clocks, you've inputted all 8 bits of your data, and the 'DATA_EN' line is pulled low, preventing any 1's getting in, so the input after this will just be 0's.
Also, we've sent 4 bits out of the shift register, and it still contains the last 4 bits of our data.
After 12 clocks, all our data has passed through the shift register, through the MUX, and to the output. The shift register now simply contains '0000'. And the CRC encoder should have the 4-bit checksum in its registers. So, we disable the CRC encoder (pull 'CRC_ENABLE' low) so it acts like a basic shift register. We also switch the 'DATA OUT' to the output of the CRC encoder, by changing the MUX's input from 1 to 0. Then the next 4 clocks just shift out the 4-bit CRC checksum to the 'DATA OUT'.
So, after 16 clocks in total, we've read in our 8 bits of data, and sent out our data, followed directly by its 4-bit CRC checksum.
So heres a crude I/O map:
CLK: T T T T T T T T T T T T T T T T
_IN d d d d d d d d X X X X X X X X
OUT 0 0 0 0 d d d d d d d d C C C C
Where 'T' is a clock tick, 'd' is a data bit, 'C@ is a checksum bit, and 'X' is 'don't care'
Hope you understand, and I hope it helps. I did a similar thing for a 12,8 Hamming encoder for error correction, although it was a tad more complicated.
Exhausted,
BuriedCode.
[/img]