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on fully digital gates
Next time, be more specific about what you are doing, what you know, and what you want to find out.
.....means dealling with CMOS/TLL 74, 4000 series chips. Are you using a CPLD? FPGA? Simulated software?
that's give me an enlightment .. i never think that wayClock in your data into the CRC encoder, and at the same time clock it in to another 4-bit shift register, which acts as a 4-bit delay.
7 webpages? are u sure? what are they? i must missed that7 webpages that have a complete schematic...
If you ask nicely, I'll draw up my own schem, and post it here.
COme On...Show Up your idea sir, Would you please draw it. ( Hope i asked well and correct)