simon111
Newbie level 4
output pad net has an illegal load
hi experts:
i am new to fpga,
i am using xilinx spartan3e and want transfer some data with cypress fx2 via slave fifo interface. i work with ise,
i write a logic circuit, i can synthesize it successfully, but i can not translate it successfully
following is my code:
and this is error message ise report.
how can i do? i have no idea
thank you in advance
Simon
hi experts:
i am new to fpga,
i am using xilinx spartan3e and want transfer some data with cypress fx2 via slave fifo interface. i work with ise,
i write a logic circuit, i can synthesize it successfully, but i can not translate it successfully
following is my code:
Code:
// ep2 -- out , wirte the image data,
// ep6 -- in , read the image data
module slave_fifo_syn(
sys_clk ,
sys_rst_n ,
usb_fifo_clk ,
usb_slwr ,
usb_slrd ,
usb_sloe ,
usb_fifo ,
usb_ad ,
usb_flaga ,
usb_flagb ,
usb_flagc ,
usb_pktend ,
usb_slcs
);
input sys_clk ; // system clk
input sys_rst_n ; // system reset, active low
input usb_flaga ; // flaga is the ep2 empty flag, active low
input usb_flagb ; // flagb is the ep6 full flag, active low
input usb_flagc ; // used
output usb_fifo_clk ; // clk for slave fifo
output usb_slwr ; // slave fifo write, active low
output usb_slrd ; // slave fifo read, active low
output usb_sloe ; // slave fifo output enable, active low
output usb_slcs ; // slave fifo chip select, active low
inout [ 7:0 ] usb_fifo ; // slave fifo data bus, bi-direction
output [ 1:0 ] usb_ad ; // ep fifo address, 0--ep2 2--dp6
output usb_pktend ; // packet end, active low
// code start here
// generate the usb fifo clk by dcm
dcm_66_33 dcm_inst (
.CLKIN_IN ( sys_clk )
,.RST_IN ( !sys_rst_n )
,.CLKFX_OUT ( usb_fifo_clk )
,.CLKIN_IBUFG_OUT ( )
,.CLK0_OUT ( )
,.LOCKED_OUT ( )
);
reg [ 8:0 ] x ;
reg [ 8:0 ] y ;
reg [17:0 ] waddr ;
wire [ 7:0 ] d ;
reg [ 7:0 ] dd ;
wire [14:0 ] ramaddr ;
reg usb_slrd ;
reg [ 7:0 ] cmd[1:3];
wire reading ;
wire ef ; // empyt flag
wire ff ; // full flag
assign ef = ~usb_flaga;
assign ff = ~usb_flagb;
assign reading = (cmd[1]==8'h01) & (cmd[2]==8'h02) & (|cmd[3]); // reading
// flagb is ep6 full flag, ep6 is a auto in endpoint
// flaga is ep2 empty flag, ep6 is a auto out endpoint
assign usb_slwr = ~usb_slrd | ff ;
assign usb_fifo = usb_flaga?d:8'bz ;
assign usb_sloe = usb_slrd ;
assign usb_ad = usb_slrd?2'h2:2'h0 ;
assign usb_pktend = 1'h1 ;
assign usb_cs = 1'h0 ;
assign ramaddr = usb_slrd?{y[6:0],x[7:0]}:waddr ;
always @(posedge usb_fifo_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
x<= #1 8'h0;
y<= #1 8'h0;
cmd[1] <= #1 8'h00 ;
cmd[2] <= #1 8'h00 ;
cmd[3] <= #1 8'h00 ;
waddr <= #1 15'h00 ;
end
else
begin
dd <= #1 d;
usb_slrd <= #1 ef;
if(~usb_slrd)
begin
if(~reading)
begin
cmd[3] <= #1 usb_fifo;
cmd[2] <= #1 cmd[3] ;
cmd[1] <= #1 cmd[2] ;
end
else
begin
waddr <= #1 waddr+15'h01;
cmd[3] <= #1 cmd[3]-8'h01;
end
end
else if(~usb_slwr)
begin
x<=#1 x+8'h01;
if(&x)
y<=#1 y+8'h01;
end
end
end
// this ram store a image,
// cypress fx2 can read/write this image
imgram ram (
.addr ( ramaddr )
,.clk ( usb_fifo_clk )
,.din ( usb_fifo )
,.dout ( d )
,.we ( reading )
);
endmoduleand this is error message ise report.
how can i do? i have no idea
thank you in advance
Simon