Help! How to make open-drain in QuartusII 4 (Cyclone FPGA)?

[mountain]

cyclon 3 open drain

These is a system:
Altera Cyclone FPGA(3.3V) and a driver IC(5V)

I want to use the FPGA output as an open drain to get the low level and a pull-up for the high.
But how can I realize it in QuartusII 4.0(Altera)?

Please give me a sample code(Verilog-HDL or VHDL, but the Verilog-HDL is better). Thank you!

 

[Ice-Tea]

how to design open drain fpga

Just asign 'Z' to your pin.

 

[cyr]

Re: Help! How to make open-drain in QuartusII 4 (Cyclone FPG

One way is like this:

output mysignal;

wire mysignal_int;

assign mysignal = (mysignal_int) ? 1'bz : 1'b0;

And then assign mysignal_int with any expression you like, and you don't have to worry about the open drain stuff in the rest of your code...

 

[mountain]

Re: Help! How to make open-drain in QuartusII 4 (Cyclone FPG

Thank you very much!

If you like, would you like to explain your method (or code)? I am a freshman.
Thank you!

 

[Black Jack]

Re: Help! How to make open-drain in QuartusII 4 (Cyclone FPG

Thank you very much!

If you like, would you like to explain your method (or code)? I am a freshman.
Thank you!

If you use schematic capture see for OPNDRN primitive.
If you use AHDL - code example bellow:

SUBDESIGN open_drain
(
   in[3..0]   :INPUT;
   hiz[3..0]  :OUTPUT;
)
BEGIN
   FOR i IN 0 TO 3 GENERATE
       hiz[i] = OPNDRN(in[i]);
   END GENERATE;