Help:how to design a unit gain Op with low power(2uA)

Hi, i need to design a unit gain Op with low power,used as a buffer,
Important parament:
(1)low power:2uA
(2)rail-to-rail input,rail-to-rail output
(3)voltage supply:5V
(4) settling time <20uS
(5) load :20pF
the 2uA current is important for me,please give me some hints,for the op structure, for some refenerce OP papers.
Thanks very much!!

Hi,

Since you want to have a settling time less than 20us, ( and I suppose that 0.1% settling time is important for you):

T=20us/8=2.5us --- > GBW= 1/2.5us=400KHz=2.51MRad/S.

I suppose you would use a very simple single-stage amplifier to obtain the highest bandwidth, so 2.51Mrad/s=gm/CL (CL=20pF) --- > gm=50uS.

So you should get a gm=50uS with a current, at most, equal 1uA. I don’t how much the gm of a transistor would be in technologies less than 0.18um, but it seems to me that getting a gm of 50mS with 1uA current is impossible (At least in a CMOS tech.)

You might be able to design the opamp with a BiCMOS technology. But even with a bipolar technology the design seems impossible to me, because I considered everything very simple (you want a R-R swing in input/output) which makes the design be more complicated and more impossible.

OpAmp

Dear OpAmp,
I have 2 question for you:
1.What do you mean about "T=20us/8" ?
2.gm=50uA/V is not difficult whith 1uA current and @0.5um CMOS process.May be we must attention the "Vdsat"(Vod),it'll very small.

Thanks a lots first!
(1)unfortunately,the process we choose is 0.18um;
(2)and 20us is the time to the accuracy > 99.9%;
(3) i also do not know why you choose the "T=20us/8"

Hi floatice and fendy,

Under the assumption of one dominant pole for the opamp, it will need about 6.9*τ (time constant)to settle within 0.1%. Adding some margin, you can choose it to be 8(or 9)*T . That's how "T=20us/8" comes.

For your design spec, you may need to use sub-threshold region models instead of square law models.

Hope it helps!

regards,
jordan76

Jordan76,
I see,is it a experiential value?
TKS

I see.
Thanks!!

I agree with the methodology that Opamp used, but am not sure the calcualtions are right:

99.9% settling -> 0.001 remaining ->ln(0.001)=-6.9. This means you need at least 6.9 time constants settling in 20uSec. (use 8x is okay) 1 time constant must be less than 2.5uSec.

GBW = 1/(2*pi*tau) = 64kHz (not 400kHz!)

GBW = gm/(2*pi*Cc). If you assume that the ouput of the amplifier is the dominant pole (single stage of gain), then Cc is the 20pF output capacitance. In this case, gm = 8uS.

If you assume that the 2uA current is carried in 6 equal parts (2x PMOS input devices, 2x NMOS input devices, 2x output legs), this makes each part about 300nA. In this case, the gm/I needed is about 27x, which is very difficult, even in subthreshold. Perhaps this can be done with some transconductance boosting.

However, if the current from the NMOS is diverted to the PMOS input pair when the NMOS can no longer be active due to low input voltage, and the opposite when the NMOS can no longer be active due to high input voltage, this makes 600nA available to transconductance. Now gm/I is more like 13x, which can be done if the input devices are in subthreshold operation.

Output slew rate limitation would still make 20uSec settling time difficult without an output stage. If all of the current is split 3 ways (one input NMOS device, one input PMOS device, and one output leg), this would produce only 600nA at the output. The time to slew 5V (rail to rail) would be 160uSec.

Here are some search keywords to help make things work:
To get high gm per current: "subthreshold MOS"
To boost gm to get better output results: "transconductance boosting"
To obtain rail-to-rail input range: "Complimentary differential pair"

what is transconductance boosting, can you give us more explain, thanks!

Excellent!

Sorry I check the forum once in a while, but fortunately Jordan76 and JPR completed and corrected my answer.

OpAmp

Transconductance boosting is used to provide higher effective transconductance in an input stage. Typically it involves the addition of some sort of positive feedback, either in the load, at the input pair, or between the load and the input pair.

The positive feedback usually consists of sensing voltages where there is small gain from the input and using that voltage to provide additional differential current into the load (or sometimes away from the load). Examples of where to sense the voltage would be at load devices in a balanced OTA, at the current injection node of a folded cascode.

Since it usually involves positive feedback, transconductance boosting must be used carefully, but it can provide benefits in gain, GBW/I ratio, gm/I ratio, and even slew rate.

Drawbacks to gm enhancement are that it often causes reduced slew rate/GBW ratio, can cause increased noise, can cause more variation in gain across process or from part-to-part and can impact stability.

Because of the drawbacks and the fact that it uses positive feedback, enhancements of 1.5x to 5x are typical.

i see! (顶)

To explain the JPR’s answer, take a look at the schematic of the one of my previously designed OpAmps. The gm is enhanced by a factor of 100 (10 because of current mirrors and 10 because of positive feedback), but keep in mind this approach may have stability problem during large swing transients.

OpAmp