Adnan86
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Hi
i want to implement , multiplication of 2 matrix. A[MxN]*B[Nxk]=C[MxK] .
I want this for implementation on FPGA with xilinx , before all i have no error with the code (on MODELSIM) .
but my output, get wrong answer , i don't where is my code wrong , so need help , plzzz
here my code :
and here my testbanch
output always wrong , i don't know why ?
I'll be so appreciate for help me .
thanks
i want to implement , multiplication of 2 matrix. A[MxN]*B[Nxk]=C[MxK] .
I want this for implementation on FPGA with xilinx , before all i have no error with the code (on MODELSIM) .
but my output, get wrong answer , i don't where is my code wrong , so need help , plzzz
here my code :
Code:
LIBRARY IEEE;
--USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
PACKAGE matrix_pkg IS
type matrix_08 is array (integer range <>, integer range <>) of signed( 7 downto 0);
type matrix_16 is array (integer range <>, integer range <>) of signed(15 downto 0);
type matrix_32 is array (integer range <>, integer range <>) of signed(31 downto 0);
type matrix_64 is array (integer range <>, integer range <>) of signed(63 downto 0);
END PACKAGE ;
LIBRARY IEEE;
USE work.matrix_pkg.all ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY MAC_matrix IS
GENERIC (M : integer:=3;
K : integer:=1;
N : integer:=2);
PORT (
a: IN matrix_16(1 to M, 1 to N); -- MxN matrix ;
b: IN matrix_16(1 to N, 1 to K); -- NxK matrix ;
clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
--flag : IN std_logic := '0' ;
c: OUT matrix_32(1 to M, 1 to K)
) ;
END MAC_matrix;
ARCHITECTURE rtl OF MAC_matrix IS
SIGNAL x_a: matrix_16(1 to M, 1 to N);
SIGNAL x_b: matrix_16(1 to N, 1 to K);
SIGNAL x_c, x_reg: matrix_32(1 to M, 1 to K);
SIGNAL flag : std_logic := '0' ;
SIGNAL ii,jj,kk : integer := 1 ;
SIGNAL sum : signed(31 downto 0) ;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'event and clk = '1') THEN
IF (reset = '1' and flag = '0') then
x_a <= (others=>(others => x"0000"));
x_b <= (others=>(others => x"0000"));
x_reg <= (others=>(others => x"00000000"));
x_c <= (others=>(others => x"00000000"));
sum <= x"00000000";
ELSIF (reset = '0' and flag = '0') THEN
x_a <= a;
x_b <= b;
flag <= '1' ;
-- END IF;
-- END IF ;
-- END process ;
-- PROCESS (clk)
-- BEGIN
-- IF (clk'event and clk = '1') THEN
ELSIF (reset = '0' and flag = '1') then
IF (ii <= M and jj <= N and kk <= K) then
x_reg(ii,kk) <= x_a(ii,jj) * x_b(jj,kk);
sum <= sum + x_reg(ii,kk);
jj <= jj + 1 ;
IF (jj > N) THEN
x_c(ii,kk) <= sum ;
END IF ;
ELSIF (ii <= M and jj > N and kk <= K) then
--ii <= ii + 1;
kk <= kk + 1 ;
jj <= 1 ;
sum <= x"00000000" ;
ELSIF (ii <= M and jj > N and kk > K) then
ii <= ii + 1;
kk <= 1 ;
jj <= 1 ;
sum <= x"00000000" ;
ELSE
c <= x_c ;
END IF ;
END IF ;
END IF;
END process;
c <= x_c ;
END rtl;and here my testbanch
Code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all ;
USE work.matrix_pkg.all ;
ENTITY Mac_matrix_tb IS
END Mac_matrix_tb;
ARCHITECTURE test_mac_behav OF Mac_matrix_tb IS
constant M : integer := 3;
constant K : integer := 1;
constant N : integer := 2;
COMPONENT MAC_matrix IS
-- GENERIC (M : integer:=M;
-- K : integer:=K;
-- N : integer:=N);
PORT (
a: IN matrix_16(1 to M, 1 to N); -- MxN matrix ;
b: IN matrix_16(1 to N, 1 to K); -- NxK matrix ;
clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
-- ready: IN STD_LOGIC;
c: OUT matrix_32(1 to M, 1 to K)
) ;
END COMPONENT;
SIGNAL a: matrix_16(1 to M, 1 to N); -- MxN matrix ;
SIGNAL b: matrix_16(1 to N, 1 to K); -- NxK matrix ;
SIGNAL clk : std_logic := '0' ;
--SIGNAL ready : std_logic := '0' ;
SIGNAL reset: STD_LOGIC := '1';
SIGNAL c: matrix_32(1 to M, 1 to K);
BEGIN
UUT : MAC_matrix
--generic map(M=>M,
-- N=>N,
-- K=>K);
PORT MAP (
a => a,
b => b,
clk=>clk,
reset => reset,
-- ready => ready,
c => c
);
clk <= NOT clk AFTER 10 NS ;
reset <= '0' AFTER 15 NS ;
--END ;
PROCESS --(clk)
BEGIN
WAIT FOR 20 NS;
a(1,1) <=x"0001";
a(1,2) <=x"0001";
a(2,1) <=x"0010";
a(2,2) <=x"0011";
a(3,1) <=x"0010";
a(3,2) <=x"0001";
b(1,1) <=x"0010";
b(2,1) <=x"0001";
WAIT FOR 10000 NS;
a(1,1) <=x"0001";
a(1,2) <=x"0001";
a(2,1) <=x"0010";
a(2,2) <=x"0011";
a(3,1) <=x"0010";
a(3,2) <=x"0001";
b(1,1) <=x"0010";
b(2,1) <=x"0001";
WAIT;
END PROCESS;
END ;output always wrong , i don't know why ?
I'll be so appreciate for help me .
thanks
Last edited: