Help for VHDL code error is No feasible entries

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_arith.ALL;
use IEEE.NUMERIC_STD.ALL; 

constant rom_width : integer := 32 ;
constant rom_length: integer := 7 ; -- 1550 integer
subtype rom_word is STD_LOGIC_VECTOR(rom_width-1 downto 0) ;
type rom_table is array (0 to rom_length-1) of rom_word ;

constant mem_width : integer := 32 ;
constant mem_length: integer := 7 ; -- 1550 integer
subtype mem_word is STD_LOGIC_VECTOR(mem_width-1 downto 0) ;
type mem_table is array (0 to mem_length-1) of mem_word ;


entity test01 is
    Port ( data_in : in  rom_table := rom ;--STD_LOGIC_VECTOR(31 downto 0);
			  clk     : in  STD_LOGIC;
			  x_diff_1: out STD_LOGIC_VECTOR(31 downto 0) );
end test01;

architecture behave of test01 is


	signal N		   : STD_LOGIC_VECTOR(11 downto 0) := "000000000111" ;
	signal ii	   : STD_LOGIC_VECTOR(11 downto 0) := "000000000001" ;
	
	[B]signal x_dif1 : mem_table ; --STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000" ;[/B]

begin

	process (clk)
		begin
			IF (clk'event AND clk = '1' ) THEN
	x_dif1(conv_integer(ii)) <= data_in( conv_integer(ii+ "000000000001" )) - data_in(conv_integer(ii)) ;
				
			end if ;
	end process ;
end bahav ;

x_dif1(conv_integer(ii)) <= data_in( conv_integer(ii+ "000000000001" )) - data_in(conv_integer(ii)) ;

signal ii : integer range 0 to 2047;

...

x_dif1(ii) <= std_logic_vector( unsigned(data_in(ii +1)) - unsigned(data_in(ii));