Help! for some advices or example of verilog module

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Matrix_YL

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HI all


It's my first time to program Asy SRAM Controller module I don't know how to deal with SRAM 's Write Timing . Especially for continuous write data to
Asy SRAM
Though it's asy SRAM without sys clock, but I want to my SRAM Controller work at 48MHz so it's can cooperate with USB!

I gave out my Asy SRAM Write Timing diagram ,I wish you can see and give me some advices ,I will appreciate you !
 

That looks like an ordinary asynchronous SRAM. You can output all those signals synchronously with your clock, except for whichever signal (BxE, WE, or CE) you want to use as write strobe. The timing diagram you posted shows BxE controlled, so I'm assuming that's the one you want, but that's not the common choice. Whichever you use, it needs to be narrower than the full cycle, to be sure you meet the various 0ns setup and hold requirements.

Here's a series of writes:
Code:
     ___ ______________ ______________ ___
ADDR ___X______________X______________X___

       ___            ___            ___
BHE- _/   \__________/   \__________/   \_

       ___            ___            ___
BLE- _/   \__________/   \__________/   \_


WE-  _____________________________________


CE-  _____________________________________

     ___ ______________ ______________ ___
DATA ___X______________X______________X___
Here is WE controlled, a more common choice:
Code:
     ___ ______________ ______________ ___
ADDR ___X______________X______________X___


BHE- _____________________________________


BLE- _____________________________________

       ___            ___            ___
WE-  _/   \__________/   \__________/   \_


CE-  _____________________________________

     ___ ______________ ______________ ___
DATA ___X______________X______________X___
Whatever you do, compare your design with the SRAM data sheet to be sure you comply with all the timing requirements.
 

Thank you echo47

How about SRAM Read Timing that I gave out ? I still have some questions about this ! I want to read out my data continuously!

SRAM's tOHA(min 3ns ) however tAA(max 10ns ) that's means I must wait for at least 3ns and begin to Read data form SRAM within tAA(max 10ns ), that's too short !

if I want to lock my data by flip latch after gave out address, how can I deal with tOHA that's I must wait for at least 3ns and same time can't over tAA .
how can I deal with my clk ? how many frequency clk need ? I use oscillator 24MHz
or if you have another advices !


thank you
 

Oh I see! You are confused by the data sheet MIN and MAX terminology, and perhaps by the difference between timing characteristics (what the chip does) and timing requirements (what you must do). I think everybody has that problem at first.

The SRAM read timing is actually very friendly. The tOHA and tAA specs are telling you this: When you change the address, the read data changes from the old value to the new value somewhere between 3ns and 10ns after your address change. During those 7ns the data is unpredictable. After that, the new read data remains valid forever unless you change the address or other inputs.

Your 24MHz clock cycle time is about 42ns. That means you can comfortably output your address on one clock, and then grab the read data on the next clock. At that time you can also output the next address.


Does anyone know of a good "how to read data sheets" tutorial to help new engineers?
 

    Matrix_YL

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