Help for research topic in PLL using CMOS

[newtale]

Hello!
I wanted to do an Individual study on PLL using CMOS technology.
Where are the areas under PLL that can I focus on which has a field of improvement in recent times?

 

[BigBoss]

There is no such "CMOS PLL" Technology. There is well known "PLL" and "Implementation Technology CMOS" that is used to build PLL sub-blocks.
So, if you know how PLL works, then you can implement this with CMOS or BiCMOS or even GaAs.No matter which process you choose, the fundamental is same.Specific attention is always paid but the principles are always same.

 

[dick_freebird]

Phase noise, frequency-agility are two perennial interests.
I doubt you'll be making any great advances in max
frequency or minimum power, that industry has not
already. Lots of CMOS PLLs out there as piece-parts
and IP blocks.

I've sometimes thought about the goodness of
breaking the classical filter and making something
else than the 1 or 2 pole linear filter. Perhaps something
like what's going on in "digital power" (changing the
control loop's architecture to chase advantages in
load-step response and stability).

But my gut says this all has been done to death
and is not terrain for much innovation, if that is
an interest or requirement. You might have to
work on how you call your topic and thesis, if it
has to satisfy such academic urges as novelty.

 

[biff44]

If it were me, i would look at the last conference proceedings of something like the IEEE Solid State Circuits, and look up the state of the art PLL papers there.

Off the top of my head, i would say any PLL operating over 60 GHz would be novel in the way you sample the frequency and control the multiplicative phase noise from the clock reference. Maybe some sort of Soliton based phase sampler on-chip?