Help for Post P&R simulation

[PigiPigi]

I design a Frequncy Meter with an 9572pc84 (Xil). I synthesized and then simulated it. It was ok (By leonard0) . Then I started Synthesis and Place and route with Ise_ . I am doing it now. When i apply my testbench to Post p&r model it doesn't respnse att all. any body can help me?

 

[linuxluo]

hi,
I think maybe after p&r your design violate timing requirement , setup/hold violation.
And simulation is Ok just after synthesis does not mean ok after p&r, becoz the result of synthesis does not include interconnect timing or does not include accurate interconnect timing.

 

[always@smart]

PigiPigi,

firstly, you can try to do functional verification, i.e. run simulation without .sdf file. if everything ok, then proceed to next.

2. run timing verification, i.e. run simulation with .sdf. if everything ok, then your design is 99% working. if not proceed to next.

3. you can try to reduce your system clock by half, and run simulation. if it's ok now. proceed to next. if not ok, reduce system clock by another half.

4. recoding and resynthesize by tighten the constraint of your design. or probably reduce your system clock requirement if possible.

Hope it helps

always@smart

 

[chiente]

Nice flow by alway@smart.

Here is just some opion;

- check STA(static timing analysis) after delay calculation.
once get the SDF, using PrimeTime or whatever tools to check timing.
(most important ** MAKE SURE THERE IS NO TIMING LOOP in design)

- If timing is fine, try turn ON/OFF timing-checking on your simulation
tools after including SDF. If no different, that means you'll need to
find your tools manual.

 

[wufengbo]

Maybe you can run a post-synthesis simulation first.

 

[PigiPigi]

Maybe you can run a post-synthesis simulation first.

I did post synthesis simulation and then post P&R sim. It's ok. I programed my device. But it doesn't work.

 

[wufengbo]

Maybe you can run a post-synthesis simulation first.

I did post synthesis simulation and then post P&R sim. It's ok. I programed my device. But it doesn't work.

Are you sure the programming file has been downloaded to the device?
In order to verify this ,Maybe you can try to implement a counter first.

 

[linuxluo]

hi,
pls check STA and the boundary timing constraints is the same as the reality.

 

[PigiPigi]

I found an error. I use an external programmer that connect to cpld board via a jtag cable. I turned off my cpld board and then program my cpld. It's successful!!!! then i verify it. It's successful again!!!! then I disconnect jtag cable. But Ise can programm my cpld and verify it again !!!! It's a serious problem. How can help me?